Krauss, Tillmann ; Wessely, Frank ; Schwalke, Udo (2018)
Reconfigurable electrostatically doped 2.5-gate planar field-effect transistors for dopant-free CMOS.
Taormina, Sizilien (09.04.2018-12.04.2018)
doi: 10.1109/DTIS.2018.8368567
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
In this paper, we demonstrate by extending TCAD simulations based on experimental data of fabricated electrostatically doped, reconfigurable planar double-gate field-effect transistors, the improved characteristics of a triple gate device design. The technological cornerstones for this general-purpose FET comprise mid-gap Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type, is interchangeable during operation by applying a control-gate voltage which significantly increases the flexibility and versatility in the design of integrated circuits.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2018 |
| Autor(en): | Krauss, Tillmann ; Wessely, Frank ; Schwalke, Udo |
| Art des Eintrags: | Bibliographie |
| Titel: | Reconfigurable electrostatically doped 2.5-gate planar field-effect transistors for dopant-free CMOS |
| Sprache: | Englisch |
| Publikationsjahr: | 31 Mai 2018 |
| Buchtitel: | 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) |
| Veranstaltungsort: | Taormina, Sizilien |
| Veranstaltungsdatum: | 09.04.2018-12.04.2018 |
| DOI: | 10.1109/DTIS.2018.8368567 |
| URL / URN: | https://doi.org/10.1109/DTIS.2018.8368567 |
| Kurzbeschreibung (Abstract): | In this paper, we demonstrate by extending TCAD simulations based on experimental data of fabricated electrostatically doped, reconfigurable planar double-gate field-effect transistors, the improved characteristics of a triple gate device design. The technological cornerstones for this general-purpose FET comprise mid-gap Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type, is interchangeable during operation by applying a control-gate voltage which significantly increases the flexibility and versatility in the design of integrated circuits. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Halbleitertechnik und Nanoelektronik |
| Hinterlegungsdatum: | 07 Jun 2018 14:17 |
| Letzte Änderung: | 07 Jun 2018 14:17 |
| PPN: | |
| Export: | |
| Suche nach Titel in: | TUfind oder in Google |
 |
Frage zum Eintrag |
Optionen (nur für Redakteure)
 |
Redaktionelle Details anzeigen |
Drucken
Impressum