2006

Pandey, S. ; Murgan, T. ; Glesner, Manfred (2006)
Energy Conscious Simultaneous Voltage Scaling and On-Chip Communication Bus Synthesis.
Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006). Nice, France (16.10.2006-18.10.2006)
Konferenzveröffentlichung, Bibliographie

Pandey, S. ; Glesner, Manfred (2006)
Energy Efficient MPSoC On-chip Communication Bus Synthesis Using Voltage Scaling Technique.
IEEE International Symposium on Circuits and Systems (ISCAS 2006). Kos, Greece (21.05.2006-24.05.2006)
doi: 10.1109/ISCAS.2006.1692940
Konferenzveröffentlichung, Bibliographie

Pandey, S. ; Glesner, Manfred (2006)
Energy Efficient Statistical On-Chip Communication Bus Synthesis for Reconfigurable Architecture.
International Conference on Field Programmable Logic and Applications (FPL 2006). Madrid, Spain (28.08.2006-30.08.2006)
doi: 10.1109/FPL.2006.311210
Konferenzveröffentlichung, Bibliographie

Murgan, T. ; Mitea, O. ; Pandey, S. ; Bacinschi, P. B. ; Glesner, Manfred (2006)
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006). Nice, France (16.10.2006-18.10.2006)
Konferenzveröffentlichung, Bibliographie

Pandey, S. ; Glesner, Manfred (2006)
Statistical On-Chip Communication Bus Synthesis and Voltage Scaling Under Timing Yield Constraint.
43rd annual Design Automation Conference (DAC '06). San Francisco, Kalifornien, USA (24.07.2006-28.07.2006)
doi: 10.1109/DAC.2006.229278
Konferenzveröffentlichung, Bibliographie

Pandey, S. ; Utlu, Nurten ; Glesner, Manfred (2006)
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.
Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006). Nice, France (16.10.2006-18.10.2006)
Konferenzveröffentlichung, Bibliographie