TU Darmstadt / ULB / TUbiblio

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters

Murgan, T. ; Mitea, O. ; Pandey, S. ; Bacinschi, P. B. ; Glesner, Manfred :
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
In: IFIP VLSI-SoC 2006 : IFIP WG 10.5 International Conference on Very Large Scale Integration System-on-Chip ; Nice, France, October 16 - 18, 2006 / sponsored by IFIP WG 10.5 ... Organised by TIMA Laboratory, Grenoble, France. [Ed. by Salvador Mir ...]. - Ge . TIMA Laboratory , Genoble
[Konferenz- oder Workshop-Beitrag], (2006)

Typ des Eintrags: Konferenz- oder Workshop-Beitrag (Keine Angabe)
Erschienen: 2006
Autor(en): Murgan, T. ; Mitea, O. ; Pandey, S. ; Bacinschi, P. B. ; Glesner, Manfred
Titel: Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters
Sprache: Englisch
Reihe: IFIP VLSI-SoC 2006 : IFIP WG 10.5 International Conference on Very Large Scale Integration System-on-Chip ; Nice, France, October 16 - 18, 2006 / sponsored by IFIP WG 10.5 ... Organised by TIMA Laboratory, Grenoble, France. [Ed. by Salvador Mir ...]. - Ge
Ort: Genoble
Verlag: TIMA Laboratory
Fachbereich(e)/-gebiet(e): Fachbereich Elektrotechnik und Informationstechnik
Hinterlegungsdatum: 20 Nov 2008 08:25
Export:

Optionen (nur für Redakteure)

Eintrag anzeigen Eintrag anzeigen