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Number of items: 6.

Hinkelmann, Heiko and Murgan, T. and Liu, G. and Zipf, Peter and Glesner, Manfred (2007):
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
In: International Workshop on Reconfigurable Communication-centric System-on-Chips (ReCoSoC), Montpellier, France 2007, [Conference or Workshop Item]

Glesner, Manfred and Murgan, T. and Hollstein, T. and Zipf, Peter and Soffke, O. and Hinkelmann, Heiko (2007):
System Design Challenges in the Nanoscale Era.
In: Scientific Bulletin of the Faculty of Electronics, Telecommunications and Informatics, Gdansk Univ. of Technology - Information Technology Series, volume 12, pages 3-14, 2007., [Article]

Pandey, S. and Murgan, T. and Glesner, Manfred (2006):
Energy Conscious Simultaneous Voltage Scaling and On-Chip Communication Bus Synthesis.
In: VLSI-SoC: Research Trends in VLSI and Systems on Chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France / Hrsg. Giovanni DeMicheli; Hrsg. Salvador Mir; Hrsg. Ricardo R, 1. Ed. - Berlin, Springer US, [Conference or Workshop Item]

Murgan, T. and Momeni, M. and Ortiz, A. and Glesner, Manfred (2006):
A High-Level Compact Pattern-Dependent Delay Model for High-Speed Point -to-Point Interconncects.
In: IEEE/ACM digest of technical papers / IEEE/ACM International Conference on Computer Aided Design, ICCAD-2006 : DoubleTree Hotel San Jose, San Jose, California, November 5 - 9, 2006. - [Piscataway, NJ : IEEE Operations Center], 2006, S. 323-328, [Piscataway, NJ, IEEE Operations Center], [Conference or Workshop Item]

Murgan, T. and Bacinschi, P. B. and Ortiz, A. G. and Glesner, Manfred (2006):
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-Wire Capacitance.
In: Integrated circuit and system design : power and timing modeling, optimization and simulation ; 16th international workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006 ; proceedings / Johan Vounckx ... (ed.). - Berlin [u.a.] : Springer, 2006, Berlin [u.a.], Springer, [Conference or Workshop Item]

Murgan, T. and Mitea, O. and Pandey, S. and Bacinschi, P. B. and Glesner, Manfred (2006):
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
In: IFIP VLSI-SoC 2006 : IFIP WG 10.5 International Conference on Very Large Scale Integration System-on-Chip ; Nice, France, October 16 - 18, 2006 / sponsored by IFIP WG 10.5 ... Organised by TIMA Laboratory, Grenoble, France. [Ed. by Salvador Mir ...]. - Ge, Genoble, TIMA Laboratory, [Conference or Workshop Item]

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