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Number of items: 6.

Blank, Claudia ; Eveking, Hans ; Levihn, Jens ; Ritter, G. (2001):
Symbolic simulation techniques - state-of-the-art and applications.
In: HLDVT '01: International High Level Design Validation and Test Workshop <6, 2001, Monterey, Calif.>; Proceedings. - Los Alamitos, Calif.: IEEE Computer Soc., 2001, Los Alamitos, Calif., IEEE Computer Soc., [Conference or Workshop Item]

Hinrichsen, Holger ; Ritter, G. ; Eveking, H. (2000):
False-path elimination and simplification of sequential acyclic descriptions with complex branching logic.
In: AAA Workshop <2000, Rocquencourt>: Proceedings, [Conference or Workshop Item]

Blank, C. ; Ritter, G. ; Hinrichsen, H. ; Eveking, H. (2000):
Formale Verifikation der Register-Allokation.
In: ITG/GI/GMM-Workshop <2000, Frankfurt>: Proceedings, [Conference or Workshop Item]

Eveking, Hans ; Hinrichsen, H. ; Ritter, G. (1999):
Automatic verification of scheduling results in high-level synthesis.
In: DATE'99: Design, Automation and Test in Europe <1999, München>; Proceedings. - Los Alamitos: IEEE, 1999, Los Alamitos, IEEE, [Conference or Workshop Item]

Hinrichsen, Holger ; Ritter, G. ; Eveking, H. (1999):
Automatische Synthese und Verifikation von RISC-Prozessoren.
In: GI/ITG/GMM-Workshop <1999, Braunschweig>: Proceedings. Hrsg.: M. Mutz, M. Lange. - Aachen: Shaker, 1999, Aachen, Shaker, [Conference or Workshop Item]

Hinrichsen, Holger ; Eveking, H. ; Ritter, G. (1999):
Formal synthesis for pipeline design.
In: DMTCS+CATS'99: International Conference on Discrete Mathematics and Theoretical Computer Science <2, 1999, Auckland>: Proceedings. - Berlin (u.a.): Springer, 1999, Berlin (u.a.), Springer, [Conference or Workshop Item]

This list was generated on Sat May 27 00:30:23 2023 CEST.