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Symbolic simulation techniques - state-of-the-art and applications.
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Hinrichsen, Holger ; Ritter, G. ; Eveking, H. (2000):
False-path elimination and simplification of sequential acyclic descriptions with complex branching logic.
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Blank, C. ; Ritter, G. ; Hinrichsen, H. ; Eveking, H. (2000):
Formale Verifikation der Register-Allokation.
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Automatic verification of scheduling results in high-level synthesis.
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Hinrichsen, Holger ; Ritter, G. ; Eveking, H. (1999):
Automatische Synthese und Verifikation von RISC-Prozessoren.
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Hinrichsen, Holger ; Eveking, H. ; Ritter, G. (1999):
Formal synthesis for pipeline design.
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