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Number of items: 10.

Schickel, Martin and Nimbler, Volker and Braun, Martin and Eveking, Hans (2006):
On Consistency and Completeness of Property-Sets : Exploiting the Property-Based Design-Process.
In: Forum on Design Languages <Darmstadt,2006>, [Conference or Workshop Item]

Glesner, Manfred and Indrusiak, Leandro Soares and Mooney, V. and Eveking, Hans (eds.) (2006):
VLSI-SOC: From Systems to Chips : IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1 - 3, 2003, Darmstadt, Germany.
200New York, Springer, ISBN 0-387-33402-5,

Abraham, J. A. and Betts, A. and Drechsler, Rolf and Eveking, Hans and Foster, H. D. and Kropf, T. and Morley, M. J. and Shiple, T. R. and Siegel, M. (2002):
Formal verification : current use and future perspectives.
In: IEEE design & test of computers, (5), 19. pp. 105-113, DOI: 10.1109/MDT.2002.1033798,

Eveking, Hans and Blank, Claudia and Krieger, Malte (2002):
Formale Verifikation eingebetteter Systeme.

Eveking, Hans and Blank, Claudia and Levihn, Jens (2002):
Korrekter Entwurf eingebetteter Systeme.
In: Eingebettete Systeme : Entwurf und Anwendungen versteckter Computer.- Darmstadt, 2002.- (Thema Forschung ; 2002,1).- S. 38-41, [Article]

Levihn, Jens and Krieger, Malte and Eveking, Hans and Blank, Claudia (2002):
MCML - a markup-language for a model-of-computation centred design and verification environment.
In: Forum on Specification and Design Languages <5, 2002, Marseille> : Proceedings ... FDL '02.- Marseille: ESIM, [Conference or Workshop Item]

Eveking, Hans (ed.) (2001):
Schwerpunktthema: Formale Verifikationsverfahren.
43,1München, Oldenbourg, [Book]

Blank, Claudia and Eveking, Hans and Levihn, Jens and Ritter, G. (2001):
Symbolic simulation techniques - state-of-the-art and applications.
In: HLDVT '01: International High Level Design Validation and Test Workshop <6, 2001, Monterey, Calif.>; Proceedings. - Los Alamitos, Calif.: IEEE Computer Soc., 2001, Los Alamitos, Calif., IEEE Computer Soc., [Conference or Workshop Item]

Eveking, Hans and Hinrichsen, H. and Ritter, G. (1999):
Automatic verification of scheduling results in high-level synthesis.
In: DATE'99: Design, Automation and Test in Europe <1999, München>; Proceedings. - Los Alamitos: IEEE, 1999, Los Alamitos, IEEE, [Conference or Workshop Item]

Eveking, Hans (1998):
Machine assisted verification.
In: Lipari Summerschool on Architecture Design and Validation Methods <1998>: Proceedings. Hrsg.: E. Börger. - Berlin (u.a.): Springer, 1998, Berlin (u.a.), Springer, [Conference or Workshop Item]

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