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Murgan, T. and Mitea, O. and Pandey, S. and Bacinschi, P. B. and Glesner, Manfred (2006):
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
Genoble, TIMA Laboratory, In: IFIP VLSI-SoC 2006 : IFIP WG 10.5 International Conference on Very Large Scale Integration System-on-Chip ; Nice, France, October 16 - 18, 2006 / sponsored by IFIP WG 10.5 ... Organised by TIMA Laboratory, Grenoble, France. [Ed. by Salvador Mir ...]. - Ge, [Conference or Workshop Item]

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