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The Application of Atomic Force Microscopy in Semiconductor Technology - Towards High-K Gate Dielectric Integration

Stefanov, Yordan (2012)
The Application of Atomic Force Microscopy in Semiconductor Technology - Towards High-K Gate Dielectric Integration.
Technische Universität Darmstadt
Dissertation, Erstveröffentlichung

Kurzbeschreibung (Abstract)

Development of semiconductor technology over the last five decades has led to aggressive scaling down of integrated circuit (IC) device dimensions. ICs have become faster, denser and more power-efficient by continuous shrinking down of the metal-oxide-semiconductor field-effect transistor (MOSFET) size and implementation of complex integration schemes using novel materials. We are steadily approaching the physical limits of scaling and along the way more and more obstacles appear that need to be overcome in order to continue further. Traditional process control and device characterization techniques are becoming insufficient for addressing these problems. Novel techniques must be implemented for obtaining information about structural and electrical properties on materials and geometries with nanometer resolution. This is particularly relevant at the present transition from silicon dioxide gate dielectrics to ones with higher dielectric permittivity – high-K dielectrics. The present work is a contribution to this search for novel suitable analytical techniques and their implementation in semiconductor technology. It exploits extensively the high resolution imaging possibilities of atomic force microscopy (AFM) as a key support technique from the selection of prospective high-K candidates to their integration into a suitable MOSFET fabrication process. Particular attention is paid to conductive atomic force microscopy (C-AFM) which offers the possibility of mapping simultaneously topography dimensions and electrical conductivity. Initially, AFM and C-AFM are used for the development and optimization of a device isolation technology that is relevant in the context of high-K dielectrics in ultra large scale integration (ULSI) ICs – shallow trench isolation (STI). For the first time, reliable detection is obtained of the common problem related to STI – nitride erosion after the chemical planarization (CMP) step. Again with the help of C-AFM, two different techniques for planarity optimization are developed and evaluated – oxide etchback and reverse nitride masking. Next, C-AFM supports the investigation of two principally different types of prospective high-K dielectric materials. First generation dual-stack dielectrics that consist of a high-K material on top of a thin interfacial silicon dioxide layer are the easier but less effective solution. C-AFM reveals imperfections in the investigated titanium oxide – silicon dioxide stacks related to the insufficient stability of such bilayer structures. Second generation high-K dielectrics in the face of epitaxial rare-earth metal oxides possess key advantages such as higher thermal stability and the possibility for engineered interface with silicon. C-AFM investigates their properties and proves the superiority of these materials. Imperfections are observed as well that show the need for growth and processing optimizations. For the first time, charge trapping is observed on the nanoscale directly on the high-K dielectric surface. Nonuniform leakages in rare-earth metal oxides grown under insufficiently optimized conditions presumably related to grain boundaries are discovered in some samples. Based on AFM measurements, predictions are made about the expected behavior of MOS devices incorporating these materials. The compatibility of epitaxial rare-earth metal oxides with standard complementary metal-oxide-semiconductor (CMOS) processing is investigated next. Incompatibility with some steps such as for example cleaning with acid-containing solutions is determined and suitable replacement steps are chosen. Changes in film properties are determined during key steps that could indicate incompatibility of the dielectrics with the standard gate-first integration scheme. In order to determine to what extent the observed microscopic changes affect macroscopic device behavior, epitaxial dielectric layers are integrated for the first time into complete devices. Rare earth metal oxide MOSFETs are fabricated into a modified gate-first process using different gate dielectrics. C-AFM is used for process control in critical steps. Electrical evaluation of the functional devices featuring praseodymium oxide (Pr2O3), including charge pumping, reveals that at this initial stage of development the high-K gate dielectric devices suffer from degraded performance when compared to SiO2 reference devices. Imperfections such as high density of interface states, susceptibility to charge trapping and gate leakages for large area devices are observed. Neodymium oxide (Nd2O3) integration after further optimization of the gate-first process fails to produce functional devices due to substantial degradation of the gate dielectric and excessive gate leakages. The MOSFET behavior for both materials as determined by macroscopic electrical characterization results is compared to AFM predictions and they coincide very well. It is concluded that the imperfections of the gate dielectrics are at least partially a result of the integration process. Analysis is carried out and critical performance-reducing steps are identified. The gate structuring by reactive ion etch (RIE), the source/drain ion implantation and the high temperature source/drain activation anneal are responsible for the dielectric degradation to the largest extent. The inseparable link between these steps and conventional processing leads to the idea of implementing an entirely different approach for gentle integration of high-K dielectrics. Once again with the help of AFM and C-AFM, a replacement gate technology (RGT) is developed and implemented for high-K gate dielectric MOS devices in order to prove this concept. By positioning the gate dielectric growth module after the source/drain implantation and anneal and avoiding the aggressive RIE through indirect gate patterning with CMP, the integration process is adapted to the sensitive high-K materials in order to preserve their as-grown state. Electrical evaluation of devices with Gd2O3 produced using RGT proves the advantage of RGT. The first integration attempt is compared to conventional fabrication technology and there are definite improvements in terms of threshold voltage stability and interface state distribution. The first RGT high-K devices still do not exhibit the mobility and low defect density of equivalent state-of-the-art SiO2 devices but this is expected considering the 40-year-long optimization history behind silicon dioxide. Further optimization is needed for epitaxial rare-earth metal oxides as well, both in terms of growth conditions and process integration.

Typ des Eintrags: Dissertation
Erschienen: 2012
Autor(en): Stefanov, Yordan
Art des Eintrags: Erstveröffentlichung
Titel: The Application of Atomic Force Microscopy in Semiconductor Technology - Towards High-K Gate Dielectric Integration
Sprache: Englisch
Referenten: Schwalke, Prof. Udo ; Riechert, Prof. Henning
Publikationsjahr: 23 März 2012
Ort: Darmstadt, Deutschland
Verlag: Darmstädter Dissertationen
Datum der mündlichen Prüfung: 30 September 2011
URL / URN: urn:nbn:de:tuda-tuprints-29314
Kurzbeschreibung (Abstract):

Development of semiconductor technology over the last five decades has led to aggressive scaling down of integrated circuit (IC) device dimensions. ICs have become faster, denser and more power-efficient by continuous shrinking down of the metal-oxide-semiconductor field-effect transistor (MOSFET) size and implementation of complex integration schemes using novel materials. We are steadily approaching the physical limits of scaling and along the way more and more obstacles appear that need to be overcome in order to continue further. Traditional process control and device characterization techniques are becoming insufficient for addressing these problems. Novel techniques must be implemented for obtaining information about structural and electrical properties on materials and geometries with nanometer resolution. This is particularly relevant at the present transition from silicon dioxide gate dielectrics to ones with higher dielectric permittivity – high-K dielectrics. The present work is a contribution to this search for novel suitable analytical techniques and their implementation in semiconductor technology. It exploits extensively the high resolution imaging possibilities of atomic force microscopy (AFM) as a key support technique from the selection of prospective high-K candidates to their integration into a suitable MOSFET fabrication process. Particular attention is paid to conductive atomic force microscopy (C-AFM) which offers the possibility of mapping simultaneously topography dimensions and electrical conductivity. Initially, AFM and C-AFM are used for the development and optimization of a device isolation technology that is relevant in the context of high-K dielectrics in ultra large scale integration (ULSI) ICs – shallow trench isolation (STI). For the first time, reliable detection is obtained of the common problem related to STI – nitride erosion after the chemical planarization (CMP) step. Again with the help of C-AFM, two different techniques for planarity optimization are developed and evaluated – oxide etchback and reverse nitride masking. Next, C-AFM supports the investigation of two principally different types of prospective high-K dielectric materials. First generation dual-stack dielectrics that consist of a high-K material on top of a thin interfacial silicon dioxide layer are the easier but less effective solution. C-AFM reveals imperfections in the investigated titanium oxide – silicon dioxide stacks related to the insufficient stability of such bilayer structures. Second generation high-K dielectrics in the face of epitaxial rare-earth metal oxides possess key advantages such as higher thermal stability and the possibility for engineered interface with silicon. C-AFM investigates their properties and proves the superiority of these materials. Imperfections are observed as well that show the need for growth and processing optimizations. For the first time, charge trapping is observed on the nanoscale directly on the high-K dielectric surface. Nonuniform leakages in rare-earth metal oxides grown under insufficiently optimized conditions presumably related to grain boundaries are discovered in some samples. Based on AFM measurements, predictions are made about the expected behavior of MOS devices incorporating these materials. The compatibility of epitaxial rare-earth metal oxides with standard complementary metal-oxide-semiconductor (CMOS) processing is investigated next. Incompatibility with some steps such as for example cleaning with acid-containing solutions is determined and suitable replacement steps are chosen. Changes in film properties are determined during key steps that could indicate incompatibility of the dielectrics with the standard gate-first integration scheme. In order to determine to what extent the observed microscopic changes affect macroscopic device behavior, epitaxial dielectric layers are integrated for the first time into complete devices. Rare earth metal oxide MOSFETs are fabricated into a modified gate-first process using different gate dielectrics. C-AFM is used for process control in critical steps. Electrical evaluation of the functional devices featuring praseodymium oxide (Pr2O3), including charge pumping, reveals that at this initial stage of development the high-K gate dielectric devices suffer from degraded performance when compared to SiO2 reference devices. Imperfections such as high density of interface states, susceptibility to charge trapping and gate leakages for large area devices are observed. Neodymium oxide (Nd2O3) integration after further optimization of the gate-first process fails to produce functional devices due to substantial degradation of the gate dielectric and excessive gate leakages. The MOSFET behavior for both materials as determined by macroscopic electrical characterization results is compared to AFM predictions and they coincide very well. It is concluded that the imperfections of the gate dielectrics are at least partially a result of the integration process. Analysis is carried out and critical performance-reducing steps are identified. The gate structuring by reactive ion etch (RIE), the source/drain ion implantation and the high temperature source/drain activation anneal are responsible for the dielectric degradation to the largest extent. The inseparable link between these steps and conventional processing leads to the idea of implementing an entirely different approach for gentle integration of high-K dielectrics. Once again with the help of AFM and C-AFM, a replacement gate technology (RGT) is developed and implemented for high-K gate dielectric MOS devices in order to prove this concept. By positioning the gate dielectric growth module after the source/drain implantation and anneal and avoiding the aggressive RIE through indirect gate patterning with CMP, the integration process is adapted to the sensitive high-K materials in order to preserve their as-grown state. Electrical evaluation of devices with Gd2O3 produced using RGT proves the advantage of RGT. The first integration attempt is compared to conventional fabrication technology and there are definite improvements in terms of threshold voltage stability and interface state distribution. The first RGT high-K devices still do not exhibit the mobility and low defect density of equivalent state-of-the-art SiO2 devices but this is expected considering the 40-year-long optimization history behind silicon dioxide. Further optimization is needed for epitaxial rare-earth metal oxides as well, both in terms of growth conditions and process integration.

Alternatives oder übersetztes Abstract:
Alternatives AbstractSprache

Die Entwicklung der Halbleitertechnologie hat in den zurückliegenden fünf Jahrzehnten zur aggressiven Verkleinerung der Bauelementdimensionen in integrierten Schaltkreisen (ICs) geführt. Durch die stetige Verkleinerung von Metall-Oxid-Halbleiter-Feldeffekt-Transistoren (MOSFETs) und durch Implementierung von hoch-komplexen Systemen unter Zuhilfenahme neuer Materialien sind ICs schneller und energieeffizienter geworden, zudem wurde die Packungsdichte erhöht. Jedoch ist man hierdurch immer näher an die physikalischen Grenzen der Skalierung gestoßen, die überwunden werden müssen, um diese Entwicklung weiter fortsetzen zu können. Mit zunehmender Verkleinerung der Bauelemente in den Nanometerbereich sind konventionelle Techniken der Prozesskontrolle und Charakterisierung immer weniger geeignet. Daher müssen neue Verfahren für die Gewinnung von Informationen über strukturelle und elektrische Eigenschaften von Materialien und Geometrien mit Nanometerauflösung entwickelt werden. Dies ist gegenwärtig, beim Übergang von Siliziumdioxid Gate-Dielektrika zu solchen mit einer höheren Dielektrizitätskonstante (sogenannten High-K-Dielektrika), besonders relevant. Die vorliegende Arbeit leistet einen Beitrag zur Auswahl geeigneter, neuartiger analytischer Methoden zur Prozesskontrolle und behandelt deren Implementierung in die Halbleitertechnologie. Hier findet die Rasterkraftmikroskopie (AFM) Anwendung, die aufgrund der hochauflösenden Abbildungsmöglichkeiten eine geeignete Technik zur Untersuchung neuartiger High-K-Dielektrika darstellt und Fragen zur Prozessintegration dieser Materialien in einen geeigneten MOSFET-Herstellungsprozess klären hilft. Besonderes Augenmerk wird auf die Rasterkraftmikroskopie mit elektrisch leitfähiger Messspitze (C-AFM) gesetzt, welches die simultane Messung von Topographie und elektrischer Leitfähigkeit an der Probenoberfläche ermöglicht. Zuerst wird die Rasterkraftmikroskopie (AFM und C-AFM) zur Entwicklung und Optimierung einer modernen Isolationstechnologie für Bauelemente, der Grabenisolation (Shallow Trench Isolation, STI) eingesetzt, die für die Integration von High-K-Dielektrika in hoch-skalierten integrierten Schaltungen (ULSI) relevant ist. Erstmalig wird der Nachweis der Nitrid-Erosion, einem bekannten Problem im Zusammenhang mit STI nach dem chemisch-mechanischen Planarisieren (CMP), in zuverlässiger Weise erreicht. Die C-AFM-Technik wird außerdem zur Entwicklung und Evaluierung von zwei unterschiedlichen Techniken zur Optimierung der Planarität erfolgreich eingesetzt, dem Oxid-Rückätz-Verfahren (oxide etchback) und der inversen Nitrid-Maskierung (reverse nitride masking). Weiterhin konnte die C-AFM-Technik für die Untersuchung von zwei grundsätzlich verschiedenen High-K-Dielektrika eingesetzt werden. Es konnte gezeigt werden, dass die erste Generation der High-Dielektrika, bestehend aus Titanoxid als High-K-Material auf einer dünnen Siliziumdioxid-Pufferschicht vom Si-Substrat getrennt, eine technologisch einfache aber elektrisch unbefriedigende Lösung darstellt. C-AFM Messungen zeigten Mängel in den untersuchten Titanoxid - Siliziumdioxid-Doppelschichtstrukturen hinsichtlich der Defektdichte und des Leckstromverhaltens. Die zweite Generation der High-K-Dielektrika, die epitaktisch gewachsenen kristallinen Seltenerd-Oxide, konnten deutlich bessere Eigenschaften mittels C-AFM nachgewiesen werden, insbesondere hinsichtlich der thermischen Stabilität. Dennoch wurden auch in diesen High-K-Materialien Unvollkommenheiten beobachtet. So konnte erstmalig der Ladungseinfang und die Generation von Einfangstellen in einem High-K-Dielektrikum im Nanometerbereich mittel C-AFM direkt an der Oberfläche beobachtet werden. Des Weiteren wird die Kompatibilität der epitaktisch gewachsenen kristallinen Seltenerd-Oxide mit Standard-CMOS-Prozessen untersucht. So wurden z.B. der Reinigung mit säurehaltigen Lösungen, Unverträglichkeiten ermittelt, die eine Neuentwicklung geeigneter Reinigungsverfahren notwendig machte. Änderungen der Filmeigenschaften wurden auch bei anderen wichtigen Prozessschritten festgestellt, die unter Umständen auf eine Unvereinbarkeit der High-K-Dielektrika mit der Standard-CMOS Prozessführung (Gate-First) hindeuten. Um zu bestimmen, inwieweit die mittels C-AFM beobachteten nanoskaligen Veränderungen im Dielektrikum das Verhalten des makroskopischen Bauelements beeinflussen, wurden epitaktische High-K-Schichten aus Praseodymoxid (Pr2O3) erstmalig vollständig in MOS-Transistoren integriert. C-AFM wurde zusätzlich zur Prozesskontrolle bei kritischen Schritten verwendet. Die elektrische Charakterisierung der voll funktionsfähigen Bauelemente mit Praseodymoxid (Pr2O3), zeigte, dass diese ersten High-K-MOSFETs deutliche Leistungseinbußen im Vergleich zur SiO2 Referenzbauelementen aufweisen. An großflächigen Bauelementen werden deutlich erhöhte Werte der Grenzflächenzustandsdichte, Gate-Leckströme und eine höhere Anfälligkeit für Ladungsträgereinfang beobachtet. Beim Versuch der Integration von anderen kristallinen Dielektrika, wie Neodymiumoxid (Nd2O3 ), konnten trotz Prozessoptimierung im Rahmen der Gate-First Technologie keine funktionierenden MOSFETs realisiert werden. Es wird gefolgert, dass die Degradation der High-K Gate-Dielektrika zumindest teilweise eine Folge des Integrationsprozesses sind. Nach Durchführung von weiteren Analysen konnten die kritischen Prozessschritte identifiziert werden. Im Wesentlichen sind die Gatestrukturierung mittels reaktivem Ionenätzen (RIE), die Source/Drain-Ionen-Implantation und das Source/Drain-Aktivierung bei hoher Temperatur für die Degradierung des Dielektrikums verantwortlich. Der untrennbare Zusammenhang zwischen diesen Schritten und der konventionellen (Gate-First) Prozessierung führte zur Entwicklung eines neuartigen Gesamtprozesskonzeptes zur schonenden Integration der High-K-Dielektrika. Unter Verwendung der Rasterkraftmikroskopie (AFM und C-AFM) wird eine sogenannte ‚Replacement-Gate-Technologie‘ (RGT) für MOS-Transistoren mit High-K-Dielektrika entwickelt und implementiert, um die Realisierbarkeit des Konzepts nachzuweisen und das Verbesserungspotential aufzuzeigen. Es konnte gezeigt werden, dass dank der geänderten Prozessfolge, in der das empfindliche High-K-Material erst nach allen aggressiven Prozessschritten eingefügt wird, die ursprünglich gute Qualität der High-K Dielektrika weitgehend erhalten bleibt. Es konnten deutliche Verbesserungen hinsichtlich der Stabilität der Einsatzspannung und der Grenflächenzustandsdichten erreicht werden.

Deutsch
Sachgruppe der Dewey Dezimalklassifikatin (DDC): 600 Technik, Medizin, angewandte Wissenschaften > 620 Ingenieurwissenschaften und Maschinenbau
Fachbereich(e)/-gebiet(e): 18 Fachbereich Elektrotechnik und Informationstechnik
18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Halbleitertechnik und Nanoelektronik
Hinterlegungsdatum: 30 Mär 2012 14:40
Letzte Änderung: 05 Mär 2013 10:00
PPN:
Referenten: Schwalke, Prof. Udo ; Riechert, Prof. Henning
Datum der mündlichen Prüfung / Verteidigung / mdl. Prüfung: 30 September 2011
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