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A Simulation Study on the Performance Improvement of CMOS Devices Using Alternative Gate Electrode Structures

Komaragiri, Rama Subrahmanyam (2006)
A Simulation Study on the Performance Improvement of CMOS Devices Using Alternative Gate Electrode Structures.
Technische Universität Darmstadt
Dissertation, Erstveröffentlichung

Kurzbeschreibung (Abstract)

The success of the microelectronics industry over more then 30 years is to a large extent based on unimaginable device scaling governed by the Moore’s law, which also resulted in performance improvements. The advances were mainly possible due to the unique properties of SiO2, which is grown by thermal oxidation and poly silicon gate technologies which substituted aluminum metal gates and enabled the self aligned gate technologies. However, the aggressive scaling of Complementary Metal Oxide Semiconductor (CMOS) devices is driving SiO2 based gate dielectrics to its physical limits as stated in the International Technology Roadmap for Semiconductors (ITRS). The scaling of device dimensions, especially the gate oxide thickness its physical limits required novel gate stack technologies, in which replacement of conventional SiO2 with a high-K material is one of them. The usage of high-K gate materials enables the scaling of the equivalent oxide thickness (EOT) of gate dielectric into sub 1 nm regime while allowing much higher physical thickness. The feasibility of scaling EOT down to sub 1 nm results in degraded performance due to the gate oxide and non-ideal gate electrode. This work mainly discusses the performance issues of the CMOS devices and possible ways to make improvements. When considering the biasing conditions of a CMOS device, the n+-poly gate of a n-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) is biased with a positive voltage and the p+-poly gate of a p-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) is biased with a negative voltage. As a result of the biasing condition, a depletion layer is formed at the gate electrode-gate oxide interface. This gate depletion is called poly gate depletion effect, results in a capacitance in series with the gate oxide capacitance. This poly gate depletion capacitance results in a decreased gate capacitance and thus results in degraded device performance. In thick oxide systems, where the gate oxide is around more than 10 nm, the gate depletion effects can be neglected as the contribution from poly gate depletion capacitance is small when compared to the gate oxide capacitance. In thin oxide systems, where the oxide thickness is less than 4 nm, the poly gate depletion effect cannot be neglected. However, degenerately doped gate electrodes can be used to suppress the poly gate depletion capacitance, by decreasing the thickness of the depletion layer formed at the gate electrode-gate oxide interface. These highly doped gate electrodes combined with thin gate oxides allow the dopants to distribute through the gate oxide and thus change the dopant distribution profile in both the gate electrode and the substrate. In ultra thin oxide systems, where the EOT is less than 2 nm, the poly gate deletion effects are unavoidable despite the gate being very highly doped. The depleted poly gate consists of parasitic charges because the ionized dopants and the parasitic charge density increases with increased doping. These parasitic gate charges act as charge centers in the gate and scatter the carries in the channel thus degrading the device performance, an effect called remote Coulomb scattering. In order to decrease the effect of remote Coulomb scattering, the parasitic gate charge density should be decreased, by reducing gate doping concentration. The reduced gate doping results in increase poly gate depletion and degrade the device performance. Thus, it is clear that the effects poly gate depletion and/or remote Coulomb scattering are unavoidable in conventionally doped gate CMOS devices. To reduce poly gate depletion and remote Coulomb scattering, the gate depletion should be completely eliminated. Metal gates provide a possible solution to eliminate poly gate depletion completely but the integration of metal gates is difficult. In order to reduce the poly gate depletion effects, an alternative gate doping scheme, where the gate is inversely doped is proposed in this work. With inversely doped gates the poly gate depletion is eliminated selectively when the device is turned on. The gate in conventional CMOS devices is generally of the same type as that of the source/drain, i.e., the NMOSFET has a n-gate and the PMOSFET has a p-gate. In an alternative gate doping scheme, the n-gate of the NMOSFET is replaced with a p-gate and vice versa for a PMOSFET. As a result, the gate is driven into accumulation when the device is turned on, thus retaining the gate capacitance at its maximum possible value of oxide capacitance. As the gate capacitance is retained at its maximum value, the device performance improves. The concept of alternative gate doping was verified by fabricating suitable hardware. Through extensive simulation studies, the concept of alternate gate doping was investigated in detail. Further simulations suggested that the concept can even be implemented in silicon on insulator devices. The simulation results suggested that the device performance can be improved significantly, thus allowing the use of poly gates even in sub 100nm regime.

Typ des Eintrags: Dissertation
Erschienen: 2006
Autor(en): Komaragiri, Rama Subrahmanyam
Art des Eintrags: Erstveröffentlichung
Titel: A Simulation Study on the Performance Improvement of CMOS Devices Using Alternative Gate Electrode Structures
Sprache: Englisch
Referenten: Schwalke, Prof. Dr. Udo ; Glesner, Prof. Dr. Manfred
Berater: Schwalke, Prof. Dr. Udo
Publikationsjahr: 6 Juli 2006
Ort: Darmstadt, Deutschland
Verlag: Darmstädter Dissertationen
Datum der mündlichen Prüfung: 6 Juli 2006
URL / URN: urn:nbn:de:tuda-tuprints-8257
Kurzbeschreibung (Abstract):

The success of the microelectronics industry over more then 30 years is to a large extent based on unimaginable device scaling governed by the Moore’s law, which also resulted in performance improvements. The advances were mainly possible due to the unique properties of SiO2, which is grown by thermal oxidation and poly silicon gate technologies which substituted aluminum metal gates and enabled the self aligned gate technologies. However, the aggressive scaling of Complementary Metal Oxide Semiconductor (CMOS) devices is driving SiO2 based gate dielectrics to its physical limits as stated in the International Technology Roadmap for Semiconductors (ITRS). The scaling of device dimensions, especially the gate oxide thickness its physical limits required novel gate stack technologies, in which replacement of conventional SiO2 with a high-K material is one of them. The usage of high-K gate materials enables the scaling of the equivalent oxide thickness (EOT) of gate dielectric into sub 1 nm regime while allowing much higher physical thickness. The feasibility of scaling EOT down to sub 1 nm results in degraded performance due to the gate oxide and non-ideal gate electrode. This work mainly discusses the performance issues of the CMOS devices and possible ways to make improvements. When considering the biasing conditions of a CMOS device, the n+-poly gate of a n-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) is biased with a positive voltage and the p+-poly gate of a p-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) is biased with a negative voltage. As a result of the biasing condition, a depletion layer is formed at the gate electrode-gate oxide interface. This gate depletion is called poly gate depletion effect, results in a capacitance in series with the gate oxide capacitance. This poly gate depletion capacitance results in a decreased gate capacitance and thus results in degraded device performance. In thick oxide systems, where the gate oxide is around more than 10 nm, the gate depletion effects can be neglected as the contribution from poly gate depletion capacitance is small when compared to the gate oxide capacitance. In thin oxide systems, where the oxide thickness is less than 4 nm, the poly gate depletion effect cannot be neglected. However, degenerately doped gate electrodes can be used to suppress the poly gate depletion capacitance, by decreasing the thickness of the depletion layer formed at the gate electrode-gate oxide interface. These highly doped gate electrodes combined with thin gate oxides allow the dopants to distribute through the gate oxide and thus change the dopant distribution profile in both the gate electrode and the substrate. In ultra thin oxide systems, where the EOT is less than 2 nm, the poly gate deletion effects are unavoidable despite the gate being very highly doped. The depleted poly gate consists of parasitic charges because the ionized dopants and the parasitic charge density increases with increased doping. These parasitic gate charges act as charge centers in the gate and scatter the carries in the channel thus degrading the device performance, an effect called remote Coulomb scattering. In order to decrease the effect of remote Coulomb scattering, the parasitic gate charge density should be decreased, by reducing gate doping concentration. The reduced gate doping results in increase poly gate depletion and degrade the device performance. Thus, it is clear that the effects poly gate depletion and/or remote Coulomb scattering are unavoidable in conventionally doped gate CMOS devices. To reduce poly gate depletion and remote Coulomb scattering, the gate depletion should be completely eliminated. Metal gates provide a possible solution to eliminate poly gate depletion completely but the integration of metal gates is difficult. In order to reduce the poly gate depletion effects, an alternative gate doping scheme, where the gate is inversely doped is proposed in this work. With inversely doped gates the poly gate depletion is eliminated selectively when the device is turned on. The gate in conventional CMOS devices is generally of the same type as that of the source/drain, i.e., the NMOSFET has a n-gate and the PMOSFET has a p-gate. In an alternative gate doping scheme, the n-gate of the NMOSFET is replaced with a p-gate and vice versa for a PMOSFET. As a result, the gate is driven into accumulation when the device is turned on, thus retaining the gate capacitance at its maximum possible value of oxide capacitance. As the gate capacitance is retained at its maximum value, the device performance improves. The concept of alternative gate doping was verified by fabricating suitable hardware. Through extensive simulation studies, the concept of alternate gate doping was investigated in detail. Further simulations suggested that the concept can even be implemented in silicon on insulator devices. The simulation results suggested that the device performance can be improved significantly, thus allowing the use of poly gates even in sub 100nm regime.
Alternatives oder übersetztes Abstract:
Alternatives AbstractSprache

Der Erfolg der Mikroelektronik über die letzten 30 Jahre ist zu einem grossen Teil auf die Skalierung der Bauelemente zurück zu führen, die dem Moore’schen Gesetz folgt und auch die Leistungsfähigkeit erhöht hat. Die Fortschritte wurden durch die einzigartigen Eigenschaften von SiO2 erzielt, das durch thermische Oxidation aufgewachsen wird, und zusätzlich durch die Verwendung von Polysiliziumgate-Technologien, die Aluminiumgates abgelöst und self-aligned gates möglich gemacht haben. Die starke Skalierung von komplementären Metall-Oxid-Halbleiter (Complementary Metal Oxide Semiconductor, CMOS)-Bauelementen treibt die SiO2-basierten Gatedielektrika an ihre physikalischen Grenzen, wie in der International Technology Roadmap for Semiconductors (ITRS) festgestellt wird. Die Skalierung der Bauelementedimensionen, inbesondere der Gateoxidedicke zu ihrer physikalischen Grenze hin erfordert neue gate stack Technologien, bei denen zum Beispiel konventionelles SiO2 durch ein high-K Material (d.h. Material mit hoher Dielektrizitätskonstante) ersetzt wird. Die Verwendung von high-K Materialien erlaubt die Skalierung der äquivalenten Oxiddicke (equivalent oxide thickness, EOT) in den Subnanometerbereich, während die physikalische Dicke viel grösser ist. Der Einsatz von high-K-Materialien mit einer EOT im Subnanometerbereich führt allerdings zu einer verringerten Leistungsfähigkeit (performance) und der nicht-idealen Gateelektrode aus Polysislizium. Die vorliegende Arbeit behandelt diese Probleme der Leistungsminderung bei CMOS-Bauelementen und diskutiert mögliche Verbesserungsansätze. Betrachtet man die spannungsbedingungen eines CMOS-Baulelementes,so liegt an einem n+- Polysiliziumgate eines n-Kanal-Metall-Oxid-Halbleiter-Feldeffekttransistors (NMOSFET) eine positive Spannung an, während an einem p+-Polysiliziumgate eines p-Kanal-Metall-Oxid-Halbleiter-Feldeffekttransistors (PMOSFET) eine negative Spannung anliegt. Dadurch bildet sich eine Verarmungsschicht an der Grenzfläche von Gateelektrode und Gateoxid. Dieser Gateverarmungseffekt, der Polygate-Verarmung genannt wird, erzeugt eine Kapazität, die mit der Gateoxidkapazität in Reihe geschaltet ist. Die Polygateverarmungs-Kapazität führt zu einer verminderten Leistungsfähigkeit des Bauelements. Im Bereich dicker Oxide, wo das Gateoxid dicker als 10nm ist, können Gateverarmungseffekte vernachlässigt werden, da der Beitrag der Polygateverarmungs-Kapazität gegenüber der Gateoxidkapazität klein ist. In Dünnoxidsystemen jedoch, wo die Gateoxiddicke 4nm und kleiner ist, kann der Polygateverarmungs-Effekt nicht vernachlässigt werden. Trotzdem können entartet dotierte Gateelektroden verwendet werden, um die Polygateverarmungs-Kapazität zu unterdrücken, indem die Dicke der Verarmungsschicht an der Grenzfläche von Gateelektrode und Gateoxid verringert wird. In Verbindung mit dünnen Gateoxiden erlauben diese hochdotierten Gateelektroden die Diffusion der Dotieratome durch das Gateoxid und verändern so das Dotierprofil sowohl in der Gateelektrode als auch im Substrat. In Ultradünnoxid-Systemen mit einer EOT von weniger als 2nm sind Polygateverarmungs-Effekte unvermeidlich, auch wenn das Gate sehr hoch dotiert ist. Das verarmte Polygate enthält parasitäre Ladungen aufgrund von ionisierten Dotierstoffatomen, und die parasitäre Ladungsdichte nimmt mit steigender Dotierung zu. Die parasitären Gateladungen wirken als Ladungszentren im Gate, an denen die Ladungsträger im Kanal gestreut werden und somit die Leistungsfähigkeit des Bauelements verringern. Dieser Effekt wird ”Remote Coulomb Scattering (RCS)” genannt. Um den Effekt des RCS zu verringern, sollte die parasitäre Gateladungsdichte reduziert werden, indem die Gatedotierkonzentration verringert wird. Damit wird klar, dass einer der beiden Effekte Polygate-Verarmung und/oder RCS in konventionell dotierten Poly-Gate-CMOSBauelementen unvermeidbar ist. Um sowohl Polygate-Verarmung als auch RCS zu reduzieren, sollte die Gateverarmung vollständig vermieden werden. Metall-Gates stellen einen möglichen Lösungsweg dar, aber die Integration von Metall-Gates ist schwierig. In der vorliegenden Arbeit wird ein alternatives Gatedotierungs-Schema vorgestellt, um Gateverarmungeffekte zu verringern, nämlich invers dotierte Gates. Mit invers dotierten Gates wird die Polygate-Verarmung selektiv unterdrückt, wenn das Bauelement angeschaltet ist. Das Gate in konventionellen CMOS-Bauelementen ist im Allgemeinen vom selben Typ wie Source und Drain, d.h. ein NMOSFET hat ein n-Gate, während ein PMOSFET ein p-Gate hat. In dem alternativen Gatedotierungs-Schema wird das n-Gate des NMOSFET durch ein p-Gate ersetzt, und umgekehrt für den PMOSFET. Folglich ist das Gate in Akkumulation, wenn das Bauelement eingeschaltet wird, sodass die Gatekapazität dem maximal erreichbaren Wert der Oxidkapazität entspricht. Die Leistungsfähigkeit des Bauelements ist dementsprechend verbessert. Das Konzept der alternativen Gatedotierung wurde durch die Herstellung geeigneter Strukturen verifiziert. Ausführliche Simulationsarbeiten dienten zur Untersuchung der alternativen Gatedotierung. Weiter führende Studien zeigten, dass dieses Konzept sich auch auf Halbleiter-auf-Isolator (Silicon on Insulator, SOI)-Bauelemente anwenden lässt. Die Simulationsergebnisse zeigten, dass die Leistungsfähigkeit der Bauelemente deutlich verbessert werden kann und Polygates somit sogar im Bereich von Gatelängen von unter 100nm benutzt werden können.

Deutsch
Freie Schlagworte: CMOS, high-K, gate electrode, performance improvement, gate architecture, gate capacitance
Fachbereich(e)/-gebiet(e): 18 Fachbereich Elektrotechnik und Informationstechnik
18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Halbleitertechnik und Nanoelektronik
Hinterlegungsdatum: 17 Okt 2008 09:22
Letzte Änderung: 05 Mär 2013 09:27
PPN:
Referenten: Schwalke, Prof. Dr. Udo ; Glesner, Prof. Dr. Manfred
Datum der mündlichen Prüfung / Verteidigung / mdl. Prüfung: 6 Juli 2006
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