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Number of items: 5.

Becker, Jürgen and Pionteck, T. and Glesner, M. (2001):
Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture.
Los Alamitos, Calif., IEEE Computer Soc., In: Computer Society Workshop on VLSI <2001, Orlando, Florida>: Proceedings. S. 41-46. - Los Alamitos, Calif.: IEEE Computer Soc., 2001, [Conference or Workshop Item]

Becker, Jürgen and Liebau, N. and Pionteck, T. and Glesner, M. (2001):
Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures.
In: International Conference on Field Programmable Logic and Applications <11, 2001, Belfast>: Proceedings, [Conference or Workshop Item]

Becker, Jürgen and Pionteck, T. and Glesner, M. (2001):
Effiziente IP-basierte Abbildungsverfahren für dynamisch-rekonfigurierbare Array-Architekturen.
In: E.I.S. Workshop: ITG/GI/GMM-Workshop Entwurf Integrierter Schaltungen und Systeme <10, 2001, Dresden>; Tagungsbd., [Conference or Workshop Item]

Kabulepa, Lukusa D. and Kella, T. and Pionteck, T. and Ludewig, Ralf and Becker, J. and Plechinger, J. and Glesner, Manfred (2001):
On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems.
Piscataway, NJ, IEEE, In: ICECS 2001:IEEE International Conference on Electronics, Circuits and Systems <8, 2001, Malta>: Proceedings. Vol. 2, S. 1069-1072. - Piscataway, NJ: IEEE, 2001, [Conference or Workshop Item]

Becker, Jürgen and Pionteck, T. and Glesner, M. (2001):
Simulation, prototyping and reconfigurable hardware realization of CDMA RAKE-receiver algorithms for flexible mobile transceivers.
In: ERSA'01: Engineering of Reconfigurable Systems and Algorithms <2001, Las Vegas, Nevada>; Proceedings, [Conference or Workshop Item]

This list was generated on Tue Oct 15 00:41:49 2019 CEST.