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Number of items: 8.

Seffrin, André (2012):
A process-algebraic approach to security-aware scheduling of dynamic partial reconfiguration on FPGA devices.
München, Dr. Hut, TU Darmstadt, ISBN 978-3-8439-0732-3,
[Ph.D. Thesis]

Seffrin, André ; Huss, Sorin (2011):
Determining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications.
In: 14. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2011),
[Conference or Workshop Item]

Seffrin, André ; Huss, Sorin (2011):
Minimal Physical Resource Allocation of Pi-Calculus Schedules to Dynamically Reconfigurable Platforms.
In: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011),
[Conference or Workshop Item]

Molter, Gregor ; Seffrin, André ; Huss, Sorin (2011):
State Space Optimization within the DEVS Model of Computation for Timing Efficiency.
In: 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'11),
[Conference or Workshop Item]

Seffrin, André ; Malipatlolla, Sunil ; Huss, Sorin (2010):
A Novel Design Flow for Tamper-Resistant Self-Healing Properties of FPGA Devices without Configuration Readback Capability.
In: IEEE International Conference on Field-Programmable Technology (ICFPT 2010),
[Conference or Workshop Item]

Seffrin, André ; Biedermann, Alexander ; Huss, Sorin (2010):
Tiny-Pi: A Novel Formal Method for Specification, Analysis, and Verification of Dynamic Partial Reconfiguration Processes.
In: 13th IEEE Forum on Specification and Design Languages (FDL 2010),
[Conference or Workshop Item]

Seffrin, André ; Biedermann, Alexander (2010):
Cellular-Array Implementations of Bio-Inspired Self-Healing Systems: State of the Art and Future Perspectives.
In: Lecture Notes in Electrical Engineering, 78., In: Design Methodologies for Secure Embedded Systems, pp. 151-170,
Springer, ISBN 978-3-64-216766-9,
[Conference or Workshop Item]

Molter, Gregor ; Seffrin, André ; Huss, Sorin (2009):
DEVS2VHDL: Automatic Transformation of XML-specified DEVS Model of Computation into Synthesizable VHDL Code.
In: 12th IEEE Forum on Specification and Design Languages (FDL 2009),
[Conference or Workshop Item]

This list was generated on Sat Sep 25 05:04:19 2021 CEST.