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Number of items: 6.

Hardieck, Martin and Lens, Dieter and Groß, Kerstin and Klingbeil, Harald and Kumm, Martin and Zipf, Peter (2018):
Signal processing hardware for single-bunch manipulation.
[Report]

Lens, Dieter and Hardieck, Martin and Groß, Kerstin and Kumm, Martin and Zipf, Peter (2017):
Signal processing development for the SIS100 bunch-by-bunch longitudinal feedback.
[Report]

Möller, Konrad and Kumm, Martin and Zipf, Peter and Groß, Kerstin and Lens, Dieter and Klingbeil, Harald (2014):
FPGA based tunable digital filtering for closed loop RF control in synchrotrons.
In: GSI Scientific Report 2013, [Report]

Kumm, Martin and Klingbeil, Harald and Zipf, Peter (2010):
An FPGA-Based Linear All-Digital Phase-Locked Loop.
In: Circuits and Systems I: Regular Papers, IEEE Transactions on, pp. 2487-2497, 57, (9), ISSN 1549-8328,
[Article]

Guntoro, Andre and Zipf, Peter and Soffke, Oliver and Klingbeil, Harald and Kumm, Martin and Glesner, Manfred (2006):
Applications - Implementation of Realtime and Highspeed Phase Detector on FPGA.
In: Reconfigurable Computing: Architectures and Applications Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Rev. Selected Papers (Lecture Notes in Computer Science , Vol. 3985), S. 1-11 Bertels, Koen; Cardoso, João M.P.; Vas, [Conference or Workshop Item]

Guntoro, Andre and Zipf, Peter and Soffke, Oliver and Klingbeil, Harald and Kumm, Martin and Glesner, Manfred (2006):
Implementation of realtime and highspeed phase detector on FPGA.
In: International Workshop on Applied Reconfigurable Computing 2006 <Delft,The Netherlands,2006> ; Reconfigurable Computing: Architectures and Applications ; 1-11 ; ISBN 3-540-36708-X, [Conference or Workshop Item]

This list was generated on Tue Oct 22 01:15:55 2019 CEST.