Guntoro, Andre ; Zipf, Peter ; Soffke, Oliver ; Klingbeil, Harald ; Kumm, Martin ; Glesner, Manfred (2006)
Applications - Implementation of Realtime and Highspeed Phase Detector on FPGA.
Architectures and Applications Second International Workshop (ARC 2006). Delft, The Netherlands (01.03.2006-03.03.2006)
doi: 10.1007/11802839_1
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
We describe the hardware implementation of a phase detector module which is used in a heavy ion accelerator for real-time digital data processing. As this high-speed real-time signal processing currently exceeds the performance of the available DSP processors, we are trying to move some functionality into dedicated hardware. We implemented the phase detection algorithm using a pipeline mechanism to process one data value in every clock cycle. We used a pipelined division operation and implemented an optimized table-based arctan as the main core to compute the phase information. As the result, we are able to process the two 400 MHz incoming data streams with low latency and minimal resource allocation.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2006 |
| Autor(en): | Guntoro, Andre ; Zipf, Peter ; Soffke, Oliver ; Klingbeil, Harald ; Kumm, Martin ; Glesner, Manfred |
| Art des Eintrags: | Bibliographie |
| Titel: | Applications - Implementation of Realtime and Highspeed Phase Detector on FPGA |
| Sprache: | Englisch |
| Publikationsjahr: | 2006 |
| Ort: | Berlin |
| Verlag: | Springer |
| Buchtitel: | Reconfigurable Computing: Architectures and Applications |
| Reihe: | Lecture Notes in Computer Science |
| Band einer Reihe: | 3985 |
| Veranstaltungstitel: | Architectures and Applications Second International Workshop (ARC 2006) |
| Veranstaltungsort: | Delft, The Netherlands |
| Veranstaltungsdatum: | 01.03.2006-03.03.2006 |
| DOI: | 10.1007/11802839_1 |
| Kurzbeschreibung (Abstract): | We describe the hardware implementation of a phase detector module which is used in a heavy ion accelerator for real-time digital data processing. As this high-speed real-time signal processing currently exceeds the performance of the available DSP processors, we are trying to move some functionality into dedicated hardware. We implemented the phase detection algorithm using a pipeline mechanism to process one data value in every clock cycle. We used a pipelined division operation and implemented an optimized table-based arctan as the main core to compute the phase information. As the result, we are able to process the two 400 MHz incoming data streams with low latency and minimal resource allocation. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik |
| Hinterlegungsdatum: | 20 Nov 2008 08:25 |
| Letzte Änderung: | 29 Nov 2024 09:38 |
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