Wirsch, Ramon ; Hochberger, Christian
Hrsg.: Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo (2021)
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA.
34th International Conference on Architecture of Computing Systems. virtual Conference (07.-08.07.2021)
doi: 10.1007/978-3-030-81682-7_8
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
Dynamic binary translation (DBT) transforms machine code at runtime into an optimzed form. DBT can have cross platform compatibility, better energy efficiency or improved performance as its goals. The goal of this work is to improve performance by executing perfomance critical parts of the binary code on a Coarse Grained Reconfigurable Array (CGRA). We show how the CGRA is integrated into the system and explain how performance critical parts of the binary code can be identified. We demonstrate the feasibility of a dynamic binary translation from RISC-V ISA to a CGRA, give details about the employed optimizations and show that the performance of a whole benchmark set can be improved by a factor of 1.7 without the need for any user intervention.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2021 |
| Herausgeber: | Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo |
| Autor(en): | Wirsch, Ramon ; Hochberger, Christian |
| Art des Eintrags: | Bibliographie |
| Titel: | Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA |
| Sprache: | Englisch |
| Publikationsjahr: | 15 Juli 2021 |
| Verlag: | Springer |
| Buchtitel: | Architecture of Computing Systems |
| Reihe: | Lecture Notes in Computer Science |
| Band einer Reihe: | 12800 |
| Veranstaltungstitel: | 34th International Conference on Architecture of Computing Systems |
| Veranstaltungsort: | virtual Conference |
| Veranstaltungsdatum: | 07.-08.07.2021 |
| DOI: | 10.1007/978-3-030-81682-7_8 |
| Kurzbeschreibung (Abstract): | Dynamic binary translation (DBT) transforms machine code at runtime into an optimzed form. DBT can have cross platform compatibility, better energy efficiency or improved performance as its goals. The goal of this work is to improve performance by executing perfomance critical parts of the binary code on a Coarse Grained Reconfigurable Array (CGRA). We show how the CGRA is integrated into the system and explain how performance critical parts of the binary code can be identified. We demonstrate the feasibility of a dynamic binary translation from RISC-V ISA to a CGRA, give details about the employed optimizations and show that the performance of a whole benchmark set can be improved by a factor of 1.7 without the need for any user intervention. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik > Rechnersysteme |
| Hinterlegungsdatum: | 09 Aug 2021 07:18 |
| Letzte Änderung: | 09 Aug 2021 07:18 |
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