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FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning

Li, Huimin ; Rieger, Phillip ; Zeitouni, Shaza ; Picek, Stjepan ; Sadeghi, Ahmad-Reza (2023)
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning.
33rd International Conference on Field-Programmable Logic and Applications. Gothenburg, Sweden (04.-08.09.2023)
doi: htps://doi.org/10.1109/FPL60245.2023.00046
Conference or Workshop Item, Bibliographie

Abstract

Federated Learning (FL) has become very popular since it enables clients to train a joint model collaboratively without sharing their private data. However, FL has been shown to be susceptible to backdoor and inference attacks. While in the former, the adversary injects manipulated updates into the aggregation process; the latter leverages clients' local models to deduce their private data. Contemporary solutions to address the security concerns of FL are either impractical for real-world deployment due to high-performance overheads or are tailored towards addressing specific threats, for instance, privacy-preserving aggregation or backdoor defenses. Given these limitations, our research delves into the advantages of harnessing the FPGA-based computing paradigm to overcome performance bottlenecks of software-only solutions while mitigating backdoor and inference attacks. We utilize FPGA-based enclaves to address inference attacks during the aggregation process of FL. We adopt an advanced backdoor-aware aggregation algorithm on the FPGA to counter backdoor attacks. We implemented and evaluated our method on Xilinx VMK-180, yielding a significant speed-up of around 300 times on the IoT-Traffic dataset and more than 506 times on the CIFAR-10 dataset.

Item Type: Conference or Workshop Item
Erschienen: 2023
Creators: Li, Huimin ; Rieger, Phillip ; Zeitouni, Shaza ; Picek, Stjepan ; Sadeghi, Ahmad-Reza
Type of entry: Bibliographie
Title: FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning
Language: English
Date: 2 November 2023
Publisher: IEEE
Book Title: Proceedings of the 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
Event Title: 33rd International Conference on Field-Programmable Logic and Applications
Event Location: Gothenburg, Sweden
Event Dates: 04.-08.09.2023
DOI: htps://doi.org/10.1109/FPL60245.2023.00046
Corresponding Links:
Abstract:

Federated Learning (FL) has become very popular since it enables clients to train a joint model collaboratively without sharing their private data. However, FL has been shown to be susceptible to backdoor and inference attacks. While in the former, the adversary injects manipulated updates into the aggregation process; the latter leverages clients' local models to deduce their private data. Contemporary solutions to address the security concerns of FL are either impractical for real-world deployment due to high-performance overheads or are tailored towards addressing specific threats, for instance, privacy-preserving aggregation or backdoor defenses. Given these limitations, our research delves into the advantages of harnessing the FPGA-based computing paradigm to overcome performance bottlenecks of software-only solutions while mitigating backdoor and inference attacks. We utilize FPGA-based enclaves to address inference attacks during the aggregation process of FL. We adopt an advanced backdoor-aware aggregation algorithm on the FPGA to counter backdoor attacks. We implemented and evaluated our method on Xilinx VMK-180, yielding a significant speed-up of around 300 times on the IoT-Traffic dataset and more than 506 times on the CIFAR-10 dataset.

Divisions: 20 Department of Computer Science
20 Department of Computer Science > System Security Lab
Profile Areas
Profile Areas > Cybersecurity (CYSEC)
Date Deposited: 27 Nov 2023 14:53
Last Modified: 27 Nov 2023 14:53
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