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Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA

Wirsch, Ramon ; Hochberger, Christian
eds.: Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo (2021)
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA.
34th International Conference on Architecture of Computing Systems. virtual Conference (07.-08.07.2021)
doi: 10.1007/978-3-030-81682-7_8
Conference or Workshop Item, Bibliographie

Abstract

Dynamic binary translation (DBT) transforms machine code at runtime into an optimzed form. DBT can have cross platform compatibility, better energy efficiency or improved performance as its goals. The goal of this work is to improve performance by executing perfomance critical parts of the binary code on a Coarse Grained Reconfigurable Array (CGRA). We show how the CGRA is integrated into the system and explain how performance critical parts of the binary code can be identified. We demonstrate the feasibility of a dynamic binary translation from RISC-V ISA to a CGRA, give details about the employed optimizations and show that the performance of a whole benchmark set can be improved by a factor of 1.7 without the need for any user intervention.

Item Type: Conference or Workshop Item
Erschienen: 2021
Editors: Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo
Creators: Wirsch, Ramon ; Hochberger, Christian
Type of entry: Bibliographie
Title: Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA
Language: English
Date: 15 July 2021
Publisher: Springer
Book Title: Architecture of Computing Systems
Series: Lecture Notes in Computer Science
Series Volume: 12800
Event Title: 34th International Conference on Architecture of Computing Systems
Event Location: virtual Conference
Event Dates: 07.-08.07.2021
DOI: 10.1007/978-3-030-81682-7_8
Abstract:

Dynamic binary translation (DBT) transforms machine code at runtime into an optimzed form. DBT can have cross platform compatibility, better energy efficiency or improved performance as its goals. The goal of this work is to improve performance by executing perfomance critical parts of the binary code on a Coarse Grained Reconfigurable Array (CGRA). We show how the CGRA is integrated into the system and explain how performance critical parts of the binary code can be identified. We demonstrate the feasibility of a dynamic binary translation from RISC-V ISA to a CGRA, give details about the employed optimizations and show that the performance of a whole benchmark set can be improved by a factor of 1.7 without the need for any user intervention.

Divisions: 18 Department of Electrical Engineering and Information Technology
18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering
18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering > Computer Systems Group
Date Deposited: 09 Aug 2021 07:18
Last Modified: 09 Aug 2021 07:18
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