Pongyupinpanich, Surapong (2012)
Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications.
Technische Universität Darmstadt
Dissertation, Erstveröffentlichung
Kurzbeschreibung (Abstract)
The challenge in designing a floating-point arithmetic co-processor/processor for scientific and engineering applications is to improve the performance, efficiency, and computational accuracy of the arithmetic unit. The arithmetic unit should efficiently support several mathematical functions corresponding to scientific and engineering computation demands. Moreover, the computations should be performed as fast as possible with a high degree of accuracy. Thus, this thesis proposes algorithm, design, architecture, and analysis of floating-point arithmetic units particularly for scientific and engineering applications which can be implemented in VLSI. Generally, performance improvements and time efficiency with hardware can be considered from the output rate and the computational latency which is the number of generated outputs per second (output/sec) and the computational times. The output rate can be increased by clock rate whereas the design and architecture of the hardware can improve the computational time, which is mostly focused on engineering practice. Obviously, in order to achieve the highest performance, the design will be based on pipeline architecture. Nevertheless, for any hardware arithmetic unit, not only the performance and time efficiency have to be examined, but also the computational accuracy and stability of the computational results have to be taken into account. Therefore, the floatingpoint arithmetic units introduced in this dissertation will be considered in their design and architecture based on pipeline, and an analysis of the hardware trade-off between the VLSI areas of complexity and computational latency. Meanwhile, the floating-point data representation is employed to improve and stabilize the computational result and accuracy of the arithmetic unit at runtime. The arithmetic units from a hardware point of view can be classified into two groups depending on hardware-based algorithms, i.e. the basic arithmetic unit and the advanced arithmetic unit. The basic arithmetic unit consists of two types of operations corresponding to the number of input operands, i.e. standard operations and non-standard operations. The standard operations are addition/subtraction and multiplication operations and the non-standard operations are product-of-sum and sum-of-product operations. The advanced arithmetic unit is frequently employed in scientific and engineering applications as elementary functions such as sine, cosine, hyperbolic sine, hyperbolic cosine, etc. The two classes of arithmetic units can be derived in hardware-based algorithmic form which is relatively easy for VLSI implementation and for analysis. The binary-tree and partial linear methods are introduced to the leading-one-detection (LOD) and the integer multiplier in order to improve the performance of the floatingpoint standard and non-standard operators. The investigation and synthesis results that are based on the pipeline architecture show that both the proposed floating-point standard and nonstandard hardware-based algorithms can be simplified for VLSI implementation. Meanwhile, with the proposed LOD and the proposed integer multiplier, the floating-point standard and non-standard operators provide both high performance and time efficiency. The advanced arithmetic functions are performed by the CORDIC algorithm, where the challenges of the CORDIC algorithm are to reduce computational latency and to improve computational accuracy. Therefore, two CORDIC methods, namely the doublerotation and triple-rotation, are proposed. Their performance, efficiency, and computational accuracy are measured, analysed, and compared with conventional CORDIC results using the Matlab/Simulink tools. The proposed CORDIC methods provide better performance, time efficiency, and computational accuracy than the conventional method, while at the same provided error constraints with few iterations. Similarly, with the same number of iterations, the proposed CORDIC methods present better computational accuracy than the conventional method. The unified micro-rotations of the proposed CORDIC methods are established and analysed in order to study the performance and efficiency based on several pipeline stages. A high precision CORDIC algorithm, based on a unified micro-rotation of the proposed CORDIC methods, is introduced where the double-rotation and triple-rotation are applied for the normal-accuracy and high-accuracy mode, respectively. The high precision CORDIC core based on fixed-point representation is designed, implemented, and analysed. The synchronization between the floating-point standard unit, non-standard unit and the fixed-point elementary functional unit is demonstrated by floating-point arithmetic accelerator architecture and also by floating-point streaming processor architecture. The Floating-to-Fixed and Fixed-to-Floating algorithms are introduced for data conversion from floating-point to fixed-point representation and from fixed-point to floatingpoint representation. Finally, the beam phase and magnitude detector that is employed in the closed-loop control system for heavy ion synchrotron application is used for verification of the proposed CORDIC methods. In the heavy ion synchrotron application, acceleration processes lead to beam signals with decreasing time periods for the pulses. Different modes of oscillation are possible. However, the current system deals with the simplest mode of oscillation, which is almost permanently presented, if no countermeasures are taken. The beam phase control system introduced here is dedicated to cases where all bunches are oscillating in phase. Therefore, the beam phase and magnitude detector is required to observe the beam oscillation for the closed-loop control system. The design of the digital phase and magnitude detector is modelled and simulated by VHDL on Model-Sim. The simulation results based on the two patterns, ”Gap voltage” and ”Beam position” generated and captured from the mathematic model and the actual ion synchrotron system, SIS18 at GSI Helmholtzzentrum Schwerionenforschung, are compared with the Matlab/Simulinks ideal results in order to verify the proposed CORDICs computation.
| Typ des Eintrags: |
Dissertation
|
| Erschienen: |
2012 |
| Autor(en): |
Pongyupinpanich, Surapong |
| Art des Eintrags: |
Erstveröffentlichung |
| Titel: |
Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications |
| Sprache: |
Englisch |
| Referenten: |
Manfred, Prof. Glesner ; Michael, Prof. Hübner ; Andreas, Prof. Binder ; Harald, Prof Klingbeil ; Hans, Prof Eveking |
| Publikationsjahr: |
20 April 2012 |
| Ort: |
Darmstadt, Germany |
|
Datum der mündlichen Prüfung: |
17 August 2012 |
| URL / URN: |
urn:nbn:de:tuda-tuprints-30910 |
| Kurzbeschreibung (Abstract): |
The challenge in designing a floating-point arithmetic co-processor/processor for scientific and engineering applications is to improve the performance, efficiency, and computational accuracy of the arithmetic unit. The arithmetic unit should efficiently support several mathematical functions corresponding to scientific and engineering computation demands. Moreover, the computations should be performed as fast as possible with a high degree of accuracy. Thus, this thesis proposes algorithm, design, architecture, and analysis of floating-point arithmetic units particularly for scientific and engineering applications which can be implemented in VLSI. Generally, performance improvements and time efficiency with hardware can be considered from the output rate and the computational latency which is the number of generated outputs per second (output/sec) and the computational times. The output rate can be increased by clock rate whereas the design and architecture of the hardware can improve the computational time, which is mostly focused on engineering practice. Obviously, in order to achieve the highest performance, the design will be based on pipeline architecture. Nevertheless, for any hardware arithmetic unit, not only the performance and time efficiency have to be examined, but also the computational accuracy and stability of the computational results have to be taken into account. Therefore, the floatingpoint arithmetic units introduced in this dissertation will be considered in their design and architecture based on pipeline, and an analysis of the hardware trade-off between the VLSI areas of complexity and computational latency. Meanwhile, the floating-point data representation is employed to improve and stabilize the computational result and accuracy of the arithmetic unit at runtime. The arithmetic units from a hardware point of view can be classified into two groups depending on hardware-based algorithms, i.e. the basic arithmetic unit and the advanced arithmetic unit. The basic arithmetic unit consists of two types of operations corresponding to the number of input operands, i.e. standard operations and non-standard operations. The standard operations are addition/subtraction and multiplication operations and the non-standard operations are product-of-sum and sum-of-product operations. The advanced arithmetic unit is frequently employed in scientific and engineering applications as elementary functions such as sine, cosine, hyperbolic sine, hyperbolic cosine, etc. The two classes of arithmetic units can be derived in hardware-based algorithmic form which is relatively easy for VLSI implementation and for analysis. The binary-tree and partial linear methods are introduced to the leading-one-detection (LOD) and the integer multiplier in order to improve the performance of the floatingpoint standard and non-standard operators. The investigation and synthesis results that are based on the pipeline architecture show that both the proposed floating-point standard and nonstandard hardware-based algorithms can be simplified for VLSI implementation. Meanwhile, with the proposed LOD and the proposed integer multiplier, the floating-point standard and non-standard operators provide both high performance and time efficiency. The advanced arithmetic functions are performed by the CORDIC algorithm, where the challenges of the CORDIC algorithm are to reduce computational latency and to improve computational accuracy. Therefore, two CORDIC methods, namely the doublerotation and triple-rotation, are proposed. Their performance, efficiency, and computational accuracy are measured, analysed, and compared with conventional CORDIC results using the Matlab/Simulink tools. The proposed CORDIC methods provide better performance, time efficiency, and computational accuracy than the conventional method, while at the same provided error constraints with few iterations. Similarly, with the same number of iterations, the proposed CORDIC methods present better computational accuracy than the conventional method. The unified micro-rotations of the proposed CORDIC methods are established and analysed in order to study the performance and efficiency based on several pipeline stages. A high precision CORDIC algorithm, based on a unified micro-rotation of the proposed CORDIC methods, is introduced where the double-rotation and triple-rotation are applied for the normal-accuracy and high-accuracy mode, respectively. The high precision CORDIC core based on fixed-point representation is designed, implemented, and analysed. The synchronization between the floating-point standard unit, non-standard unit and the fixed-point elementary functional unit is demonstrated by floating-point arithmetic accelerator architecture and also by floating-point streaming processor architecture. The Floating-to-Fixed and Fixed-to-Floating algorithms are introduced for data conversion from floating-point to fixed-point representation and from fixed-point to floatingpoint representation. Finally, the beam phase and magnitude detector that is employed in the closed-loop control system for heavy ion synchrotron application is used for verification of the proposed CORDIC methods. In the heavy ion synchrotron application, acceleration processes lead to beam signals with decreasing time periods for the pulses. Different modes of oscillation are possible. However, the current system deals with the simplest mode of oscillation, which is almost permanently presented, if no countermeasures are taken. The beam phase control system introduced here is dedicated to cases where all bunches are oscillating in phase. Therefore, the beam phase and magnitude detector is required to observe the beam oscillation for the closed-loop control system. The design of the digital phase and magnitude detector is modelled and simulated by VHDL on Model-Sim. The simulation results based on the two patterns, ”Gap voltage” and ”Beam position” generated and captured from the mathematic model and the actual ion synchrotron system, SIS18 at GSI Helmholtzzentrum Schwerionenforschung, are compared with the Matlab/Simulinks ideal results in order to verify the proposed CORDICs computation. |
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Alternatives oder übersetztes Abstract: |
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Alternatives Abstract | Sprache |
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Beim Entwurf arithmetischer Prozessoren oder Koprozessoren für wissenschaftliches Rechnen liegt die Herausforderung darin, Rechenleistung, Effizienz, und numerische Genauigkeit zu maximieren. Derartige arithmetische Einheiten sollen mathematische Funktionen, die in wissenschaftlichen und technischen Anwendungen häufig benötigt werden, effizient unterstützen. Natürlich sollen sie Berechnungen so schnell wie möglich und mit hoher Genauigkeit durchführen. Die vorliegende Arbeit stellt deshalb Algorithmen und Architekturen für arithmetische Gleitkomma-Einheiten vor, die besonders für wissenschaftliches Rechnen geeignet sind. Die vorgestellten Architekturen sind zur Umsetzung in hochintegrierte (VLSI-)Schaltungen geeignet. Allgemeine Kenngrößen zur Beurteilung arithmetischer Einheiten sind Durchsatz und Latenz. Der Durchsatz ist die pro Zeiteinheit verarbeitete Datenmenge, die Latenz die zur Verarbeitung eines Datums benötigte Zeit. Der Durchsatz kann gesteigert werden, indem die Taktrate einer synchron getakteten Schaltung erhöht wird, während die Architektur Einfluss auf die Latenz hat. Zum Erreichen höchster Rechenleistung werden Pipeline-Architekturen verwendet. Bei den in der vorliegenden Arbeit vorgestellten Architekturen handelt es sich deshalb stets um Pipeline-Architekturen und es wird ein Kompromiss (Trade-Off ) zwischen der Komplexität einer Architektur und ihrer Latenz gesucht. Jedoch müssen bei der Beurteilung arithmetischer Einheiten nicht nur die Rechenleistung, sondern auch die numerische Genauigkeit und die Stabilität der implementierten Algorithmen betrachtet werden. In den betrachteten Architekturen kommt deshalb die Gleitkomma-Zahlendarstellung zum Einsatz um die numerische Genauigkeit und Stabilität zu verbessern. Die in der vorliegenden Arbeit betrachteten arithmetische Einheiten werden abhängig von den implementierten Algorithmen in zwei Klassen eingeteilt, nämlich in einfache und fortgeschrittene Einheiten. Einfache Einheiten implementieren zwei Klassen von Operationen, nämlich Standard- und Nichtstandard-Operationen. Standard-Operationen sind Addition, Subtraktion und Multiplikation; Nichtstandard-Operationen sind Product of Sums und Sum of Products. Fortgeschrittene Einheiten implementieren zusätzlich Funktionen, die in wissenschaftlichen und technischen Anwendungen häufig benötigt werden, wie beispielsweise die trigonometrischen (Sinus, Kosinus usw.) und hyperbolischen (Hyperbelsinus, Hyperbelkosinus usw.) Funktionen. Beide Arten von Einheiten eignen sich gut zur Umsetzung in hochintegrierte (VLSI-)Schaltungen. Die vorliegende Arbeit führt einen Bin¨arbaum-Ansatz zur Erkennung der führenden von Null verschiedenen Binärziffer (Leading-One-Detection, LOD) und partiell lineare Methoden zur Ganzzahlmultiplikation ein, um die Rechenleistung der Standard- und Nichtstandard-Operationen zu verbessern. Es wird gezeigt, dass die weitere Vereinfachung beider Arten von Operationen zwecks leichterer Umsetzung in hochintegrierte (VLSI-)Schaltungen möglich ist. Sowohl Durchsatz als auch Latenz der Standard- und Nichtstandard-Operationen wird durch diese Maßnahmen verbessert. Zur Implementierung der fortgeschrittenen Funktionen kommt der CORDIC-Algorithmus zum Einsatz. Die Herausforderung besteht dabei darin, die Latenz des Algorithmus’ zu verringern und seine numerische Genauigkeit zu verbessern. Aus diesem Grund werden zwei Weiterentwicklungen des CORDIC-Grundalgorithmus’ betrachtet, nämlich die Doppel- und die Dreifachrotation (double-rotation bzw. triple-rotation). Die Rechenleistung und Genauigkeit beider Varianten wurde analysiert und mit den Ergebnissen des konventionellen CORDIC-Algorithmus’ verglichen; dazu wurden Simulationen in MATLAB durchgeführt. Die eingeführten Weiterentwicklungen des CORDIC-Algorithmus’ bieten eine bessere Genauigkeit als der konventionelle Algorithmus; bei gleicher Genauigkeit erfordern sie eine geringere Anzahl von Iterationen und bieten somit eine geringere Latenz. Die verschiedenen Varianten des CORDIC-Algorithmus werden hinsichtlich ihrer effizienten Umsetzung in eine Pipeline-Architektur verglichen. Darauf aufbauend wird eine hochpr¨azise CORDIC-Funktionseinheit entwickelt, welche zwei Rechenmodi (normale und hohe Genauigkeit) bietet und dafür die Doppel- bzw. die Dreifachrotation nutzt. Diese Funktionseinheit basiert auf einer Festkomma-Zahlendarstellung; daher werden Hilfsfunktionen zur Konvertierung zwischen Gleitkomma- und Festkommadarstellung (Float-to-Fixed und Fixed-to-Float) eingeführt. Das Zusammenspiel zwischen Gleitkomma-Standard- und -Nichtstandard-Operationen und der Festkomma-CORDIC Funktionseinheit wird demonstriert, indem diese Einheiten sowohl in einen arithmetischen Koprozessor zur Beschleunigung wissenschaftlicher Rechnungen als auch in einen anwendungsspezifischen Prozessor zur Verarbeitung von Streaming-Daten integriert werden. Abschließend wird zur Verifikation der vorgestellten CORDIC-Algorithmen ein Phasendetektor für die Strahlphasenregelung eines Schwerionensynchrotrons vorgestellt. In einem Schwerionensynchrotron zirkulieren Teilchenpakete, so genannte Bunches. Unter gewissen Umständen kann es zu kohärenten Schwingungen der einzelnen Teilchen innerhalb eines Bunches kommen. Verschiedene Schwingungsmoden können dabei auftreten. Diese Schwingungen sind unerwünscht, weswegen eine Strahlphasenregelung eingesetzt wird, um diese Schwingungen zu dämpfen. Dabei wird zunächst nur der einfachste Mode betrachtet, bei dem alle Bunches gleichphasig schwingen und sich die Bunch-Form nicht verändert. Der Phasendetektor misst die Phasendifferenz zwischen zwei hochfrequenten Signalen, dem Strahlstrom und der Beschleunigungsspannung. Die Strahlphasenregelung ist bestrebt, Schwankungen dieser Phasendifferenz zu dämpfen. Der Phasendetektor wurde in der Hardware-Beschreibungssprache VHDL modelliert und mit ModelSim simuliert. Als Stimuli (Beschleunigungsspannung und Strahlstrom) der Simulation wurden sowohl Simulationsergebnisse eines abstrakten Modells eines Schwerionen-Synchrotrons als auch Messdaten von Maschinenexperimenten am SIS18 des GSI Helmholtzzentrum für Schwerionenforschung verwendet. Die Ausgangssignale des VHDL-Modells werden mit anderen, mit MATLAB durchgeführten Simulationen verglichen und so der CORDIC-Algorithmus verifiziert. | Deutsch |
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| Schlagworte: |
| Einzelne Schlagworte | Sprache |
|---|
| Floating-point adder, Floating-point multiplier, Floating-point divider, Vector rotation, CORDIC, Streaming computation processor and floating-point co-processor | Englisch |
|
| Sachgruppe der Dewey Dezimalklassifikatin (DDC): |
600 Technik, Medizin, angewandte Wissenschaften > 620 Ingenieurwissenschaften und Maschinenbau |
| Fachbereich(e)/-gebiet(e): |
18 Fachbereich Elektrotechnik und Informationstechnik |
| Hinterlegungsdatum: |
14 Nov 2012 08:24 |
| Letzte Änderung: |
05 Mär 2013 10:03 |
| PPN: |
|
| Referenten: |
Manfred, Prof. Glesner ; Michael, Prof. Hübner ; Andreas, Prof. Binder ; Harald, Prof Klingbeil ; Hans, Prof Eveking |
|
Datum der mündlichen Prüfung / Verteidigung / mdl. Prüfung: |
17 August 2012 |
| Schlagworte: |
| Einzelne Schlagworte | Sprache |
|---|
| Floating-point adder, Floating-point multiplier, Floating-point divider, Vector rotation, CORDIC, Streaming computation processor and floating-point co-processor | Englisch |
|
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