Kolesnikov, Vladimir ; Schneider, Thomas (2013)
Secure Function Evaluation Techniques for Circuits Containing XOR Gates with Applications to Universal Circuits.
Norm, Patent, Standard, Bibliographie
Kurzbeschreibung (Abstract)
An embodiment of the present invention provides a method that minimizes the number of entries required in a garbled circuit associated with secure function evaluation of a given circuit. Exclusive OR (XOR) gates are evaluated in accordance with an embodiment of the present invention without the need of associated entries in the garbled table to yield minimal computational and communication effort. This improves the performance of SFE evaluation. Another embodiment of the present invention provides a method that replaces regular gates with more efficient constructions containing XOR gates in an implementation of a Universal Circuit, and circuits for integer addition and multiplication, thereby maximizing the performance improvement provided by the above.
| Typ des Eintrags: | Norm, Patent, Standard |
|---|---|
| Erschienen: | 2013 |
| Autor(en): | Kolesnikov, Vladimir ; Schneider, Thomas |
| Art des Eintrags: | Bibliographie |
| Titel: | Secure Function Evaluation Techniques for Circuits Containing XOR Gates with Applications to Universal Circuits |
| Sprache: | Englisch |
| Publikationsjahr: | 14 Mai 2013 |
| Patent-Nummer: | US 8,443,205 B2 |
| Kurzbeschreibung (Abstract): | An embodiment of the present invention provides a method that minimizes the number of entries required in a garbled circuit associated with secure function evaluation of a given circuit. Exclusive OR (XOR) gates are evaluated in accordance with an embodiment of the present invention without the need of associated entries in the garbled table to yield minimal computational and communication effort. This improves the performance of SFE evaluation. Another embodiment of the present invention provides a method that replaces regular gates with more efficient constructions containing XOR gates in an implementation of a Universal Circuit, and circuits for integer addition and multiplication, thereby maximizing the performance improvement provided by the above. |
| Zusätzliche Informationen: | Patent Application: 20090175443; Expired 21.06.2021 |
| Fachbereich(e)/-gebiet(e): | 20 Fachbereich Informatik 20 Fachbereich Informatik > EC SPRIDE 20 Fachbereich Informatik > EC SPRIDE > Engineering Cryptographic Protocols (am 01.03.18 aufgegangen in Praktische Kryptographie und Privatheit) |
| Hinterlegungsdatum: | 25 Jun 2012 14:08 |
| Letzte Änderung: | 06 Aug 2024 08:29 |
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