Pandey, S. ; Glesner, Manfred (2006)
Energy Efficient Statistical On-Chip Communication Bus Synthesis for Reconfigurable Architecture.
International Conference on Field Programmable Logic and Applications (FPL 2006). Madrid, Spain (28.08.2006-30.08.2006)
doi: 10.1109/FPL.2006.311210
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
In a reconfigurable computing system, some of the on-chip modules can be configured partially to run several applications in a single chip. Due to this feature of partial reconfiguration, the size of data to be transferred among the on-chip modules is random in nature. This paper proposes a method to synthesize an energy efficient on-chip communication bus width and number buses for a reconfigurable architecture. The randomness of data for such an architecture is modeled as a normally distributed random variable. The slack is exploited to maximize sharing of buses and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of communication bus. The resulting synthesis problem is relaxed to the quadratic optimization problem and is solved efficiently using a convex optimization tool. The experimental result shows the synthesis of bus width and number of buses with reduced communication energy for different variability of data size.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2006 |
| Autor(en): | Pandey, S. ; Glesner, Manfred |
| Art des Eintrags: | Bibliographie |
| Titel: | Energy Efficient Statistical On-Chip Communication Bus Synthesis for Reconfigurable Architecture |
| Sprache: | Englisch |
| Publikationsjahr: | 2006 |
| Ort: | Piscataway, NJ |
| Verlag: | IEEE |
| Buchtitel: | 2006 International Conference on Field Programmable Logic and Applications |
| Veranstaltungstitel: | International Conference on Field Programmable Logic and Applications (FPL 2006) |
| Veranstaltungsort: | Madrid, Spain |
| Veranstaltungsdatum: | 28.08.2006-30.08.2006 |
| DOI: | 10.1109/FPL.2006.311210 |
| Kurzbeschreibung (Abstract): | In a reconfigurable computing system, some of the on-chip modules can be configured partially to run several applications in a single chip. Due to this feature of partial reconfiguration, the size of data to be transferred among the on-chip modules is random in nature. This paper proposes a method to synthesize an energy efficient on-chip communication bus width and number buses for a reconfigurable architecture. The randomness of data for such an architecture is modeled as a normally distributed random variable. The slack is exploited to maximize sharing of buses and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of communication bus. The resulting synthesis problem is relaxed to the quadratic optimization problem and is solved efficiently using a convex optimization tool. The experimental result shows the synthesis of bus width and number of buses with reduced communication energy for different variability of data size. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik |
| Hinterlegungsdatum: | 20 Nov 2008 08:25 |
| Letzte Änderung: | 22 Nov 2024 10:17 |
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