Pandey, S. ; Glesner, Manfred (2006)
Energy Efficient MPSoC On-chip Communication Bus Synthesis Using Voltage Scaling Technique.
IEEE International Symposium on Circuits and Systems (ISCAS 2006). Kos, Greece (21.05.2006-24.05.2006)
doi: 10.1109/ISCAS.2006.1692940
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
This paper presents an energy efficient on-chip communication synthesis for shared bus based architecture. An assumption for the synthesis is that a system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. The problem of communication synthesis is modeled in NLP (nonlinear programming), which finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The supply voltage is scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 44.6% by scaling its supply voltage.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2006 |
| Autor(en): | Pandey, S. ; Glesner, Manfred |
| Art des Eintrags: | Bibliographie |
| Titel: | Energy Efficient MPSoC On-chip Communication Bus Synthesis Using Voltage Scaling Technique |
| Sprache: | Deutsch |
| Publikationsjahr: | 2006 |
| Ort: | Piscataway |
| Verlag: | IEEE |
| Buchtitel: | 2006 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Veranstaltungstitel: | IEEE International Symposium on Circuits and Systems (ISCAS 2006) |
| Veranstaltungsort: | Kos, Greece |
| Veranstaltungsdatum: | 21.05.2006-24.05.2006 |
| DOI: | 10.1109/ISCAS.2006.1692940 |
| Kurzbeschreibung (Abstract): | This paper presents an energy efficient on-chip communication synthesis for shared bus based architecture. An assumption for the synthesis is that a system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. The problem of communication synthesis is modeled in NLP (nonlinear programming), which finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The supply voltage is scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 44.6% by scaling its supply voltage. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik |
| Hinterlegungsdatum: | 20 Nov 2008 08:25 |
| Letzte Änderung: | 22 Nov 2024 10:28 |
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