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High level Hardware/Software Communication Estimation in Shared Memory Architecture

Pandey, Sujan and Zimmer, Heiko and Glesner, Manfred and Mühlhäuser, Max (2005):
High level Hardware/Software Communication Estimation in Shared Memory Architecture.
pp. 37-40, IEEE, IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, 23.-26.05, ISSN 0271-4302,
DOI: 10.1109/ISCAS.2005.1464518,
[Conference or Workshop Item]

Abstract

This paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of a SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for

different bus widths. From the estimated figures we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system.

Item Type: Conference or Workshop Item
Erschienen: 2005
Creators: Pandey, Sujan and Zimmer, Heiko and Glesner, Manfred and Mühlhäuser, Max
Title: High level Hardware/Software Communication Estimation in Shared Memory Architecture
Language: English
Abstract:

This paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of a SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for

different bus widths. From the estimated figures we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system.

Publisher: IEEE
Divisions: 18 Department of Electrical Engineering and Information Technology
18 Department of Electrical Engineering and Information Technology > Integrierte Schaltungen und Systeme
20 Department of Computer Science
20 Department of Computer Science > Telecooperation
Event Title: IEEE International Symposium on Circuits and Systems (ISCAS 2005)
Event Location: Kobe, Japan
Event Dates: 23.-26.05
Date Deposited: 20 Nov 2008 08:23
DOI: 10.1109/ISCAS.2005.1464518
Additional Information:

Co-sponsored by the Institute of Electrical and Electronics Engineers, Circuits and Systems Society

Identification Number: Pandey05High
License: [undefiniert]
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