Pandey, Sujan ; Zimmer, Heiko ; Glesner, Manfred ; Mühlhäuser, Max (2005)
High level Hardware/Software Communication Estimation in Shared Memory Architecture.
IEEE International Symposium on Circuits and Systems (ISCAS 2005). Kobe, Japan (23.05.-26.05.2005)
doi: 10.1109/ISCAS.2005.1464518
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
This paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of a SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for different bus widths. From the estimated figures we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2005 |
| Autor(en): | Pandey, Sujan ; Zimmer, Heiko ; Glesner, Manfred ; Mühlhäuser, Max |
| Art des Eintrags: | Bibliographie |
| Titel: | High level Hardware/Software Communication Estimation in Shared Memory Architecture |
| Sprache: | Englisch |
| Publikationsjahr: | 2005 |
| Ort: | Kobe, Japan |
| Verlag: | IEEE |
| Veranstaltungstitel: | IEEE International Symposium on Circuits and Systems (ISCAS 2005) |
| Veranstaltungsort: | Kobe, Japan |
| Veranstaltungsdatum: | 23.05.-26.05.2005 |
| DOI: | 10.1109/ISCAS.2005.1464518 |
| Kurzbeschreibung (Abstract): | This paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of a SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for different bus widths. From the estimated figures we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system. |
| Zusätzliche Informationen: | Co-sponsored by the Institute of Electrical and Electronics Engineers, Circuits and Systems Society |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Integrierte Schaltungen und Systeme 20 Fachbereich Informatik 20 Fachbereich Informatik > Telekooperation |
| Hinterlegungsdatum: | 20 Nov 2008 08:23 |
| Letzte Änderung: | 25 Apr 2024 09:07 |
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