Hoyer, Ingo ; Utz, Alexander ; Lüdecke, André ; Kappert, Holger ; Rohr, Maurice ; Hoog Antink, Christoph ; Seidl, Karsten (2023)
Design of Hardware Accelerators for Optimized and Quantized Neural Networks to Detect Atrial Fibrillation in Patch ECG Device with RISC-V.
In: Sensors, 23 (5)
doi: 10.3390/s23052703
Artikel, Bibliographie

Kurzbeschreibung (Abstract)

Atrial Fibrillation (AF) is one of the most common heart arrhythmias. It is known to cause up to 15% of all strokes. In current times, modern detection systems for arrhythmias, such as single-use patch electrocardiogram (ECG) devices, have to be energy efficient, small, and affordable. In this work, specialized hardware accelerators were developed. First, an artificial neural network (NN) for the detection of AF was optimized. Special attention was paid to the minimum requirements for the inference on a RISC-V-based microcontroller. Hence, a 32-bit floating-point-based NN was analyzed. To reduce the silicon area needed, the NN was quantized to an 8-bit fixed-point datatype (Q7). Based on this datatype, specialized accelerators were developed. Those accelerators included single-instruction multiple-data (SIMD) hardware as well as accelerators for activation functions such as sigmoid and hyperbolic tangents. To accelerate activation functions that require the e-function as part of their computation (e.g., softmax), an e-function accelerator was implemented in the hardware. To compensate for the losses of quantization, the network was expanded and optimized for run-time and memory requirements. The resulting NN has a 7.5% lower run-time in clock cycles (cc) without the accelerators and 2.2 percentage points (pp) lower accuracy compared to a floating-point-based net, while requiring 65% less memory. With the specialized accelerators, the inference run-time was lowered by 87.2% while the F1-Score decreased by 6.1 pp. Implementing the Q7 accelerators instead of the floating-point unit (FPU), the silicon area needed for the microcontroller in 180 nm-technology is below 1 mm².

Typ des Eintrags:	Artikel
Erschienen:	2023
Autor(en):	Hoyer, Ingo ; Utz, Alexander ; Lüdecke, André ; Kappert, Holger ; Rohr, Maurice ; Hoog Antink, Christoph ; Seidl, Karsten
Art des Eintrags:	Bibliographie
Titel:	Design of Hardware Accelerators for Optimized and Quantized Neural Networks to Detect Atrial Fibrillation in Patch ECG Device with RISC-V
Sprache:	Englisch
Publikationsjahr:	2023
Ort:	Darmstadt
Verlag:	MDPI
Titel der Zeitschrift, Zeitung oder Schriftenreihe:	Sensors
Jahrgang/Volume einer Zeitschrift:	23
(Heft-)Nummer:	5
Kollation:	17 Seiten
DOI:	10.3390/s23052703
Zugehörige Links:	TUprints Zweitveröffentlichung
Kurzbeschreibung (Abstract):	Atrial Fibrillation (AF) is one of the most common heart arrhythmias. It is known to cause up to 15% of all strokes. In current times, modern detection systems for arrhythmias, such as single-use patch electrocardiogram (ECG) devices, have to be energy efficient, small, and affordable. In this work, specialized hardware accelerators were developed. First, an artificial neural network (NN) for the detection of AF was optimized. Special attention was paid to the minimum requirements for the inference on a RISC-V-based microcontroller. Hence, a 32-bit floating-point-based NN was analyzed. To reduce the silicon area needed, the NN was quantized to an 8-bit fixed-point datatype (Q7). Based on this datatype, specialized accelerators were developed. Those accelerators included single-instruction multiple-data (SIMD) hardware as well as accelerators for activation functions such as sigmoid and hyperbolic tangents. To accelerate activation functions that require the e-function as part of their computation (e.g., softmax), an e-function accelerator was implemented in the hardware. To compensate for the losses of quantization, the network was expanded and optimized for run-time and memory requirements. The resulting NN has a 7.5% lower run-time in clock cycles (cc) without the accelerators and 2.2 percentage points (pp) lower accuracy compared to a floating-point-based net, while requiring 65% less memory. With the specialized accelerators, the inference run-time was lowered by 87.2% while the F1-Score decreased by 6.1 pp. Implementing the Q7 accelerators instead of the floating-point unit (FPU), the silicon area needed for the microcontroller in 180 nm-technology is below 1 mm².
Freie Schlagworte:	atrial fibrillation, artificial intelligence, quantization, neural networks, RISC-V
Zusätzliche Informationen:	This article belongs to the Special Issue Digital Remote Healthcare Monitoring: Non-invasive Sensor Technology and AI/ML Techniques
Sachgruppe der Dewey Dezimalklassifikatin (DDC):	600 Technik, Medizin, angewandte Wissenschaften > 610 Medizin, Gesundheit 600 Technik, Medizin, angewandte Wissenschaften > 620 Ingenieurwissenschaften und Maschinenbau
Fachbereich(e)/-gebiet(e):	18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Künstlich intelligente Systeme der Medizin (KISMED)
Hinterlegungsdatum:	02 Aug 2024 12:51
Letzte Änderung:	02 Aug 2024 12:51
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Verfügbare Versionen dieses Eintrags

• Design of Hardware Accelerators for Optimized and Quantized Neural Networks to Detect Atrial Fibrillation in Patch ECG Device with RISC-V. (deposited 11 Apr 2023 11:40)
  • Design of Hardware Accelerators for Optimized and Quantized Neural Networks to Detect Atrial Fibrillation in Patch ECG Device with RISC-V. (deposited 02 Aug 2024 12:51) [Gegenwärtig angezeigt]

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