Ismail, Khaled A. ; Ghany, Mohamed A. Abd El (2022)
Survey on Machine Learning Algorithms Enhancing the Functional Verification Process.
In: Electronics, 10 (21)
doi: 10.3390/electronics10212688
Artikel, Bibliographie

Kurzbeschreibung (Abstract)

The continuing increase in functional requirements of modern hardware designs means the traditional functional verification process becomes inefficient in meeting the time-to-market goal with sufficient level of confidence in the design. Therefore, the need for enhancing the process is evident. Machine learning (ML) models proved to be valuable for automating major parts of the process, which have typically occupied the bandwidth of engineers; diverting them from adding new coverage metrics to make the designs more robust. Current research of deploying different (ML) models prove to be promising in areas such as stimulus constraining, test generation, coverage collection and bug detection and localization. An example of deploying artificial neural network (ANN) in test generation shows 24.5× speed up in functionally verifying a dual-core RISC processor specification. Another study demonstrates how k-means clustering can reduce redundancy of simulation trace dump of an AHB-to-WHISHBONE bridge by 21%, thus reducing the debugging effort by not having to inspect unnecessary waveforms. The surveyed work demonstrates a comprehensive overview of current (ML) models enhancing the functional verification process from which an insight of promising future research areas is inferred.

Typ des Eintrags:	Artikel
Erschienen:	2022
Autor(en):	Ismail, Khaled A. ; Ghany, Mohamed A. Abd El
Art des Eintrags:	Bibliographie
Titel:	Survey on Machine Learning Algorithms Enhancing the Functional Verification Process
Sprache:	Englisch
Publikationsjahr:	2022
Verlag:	MDPI
Titel der Zeitschrift, Zeitung oder Schriftenreihe:	Electronics
Jahrgang/Volume einer Zeitschrift:	10
(Heft-)Nummer:	21
Kollation:	24 Seiten
DOI:	10.3390/electronics10212688
Zugehörige Links:	TUprints Zweitveröffentlichung
Kurzbeschreibung (Abstract):	The continuing increase in functional requirements of modern hardware designs means the traditional functional verification process becomes inefficient in meeting the time-to-market goal with sufficient level of confidence in the design. Therefore, the need for enhancing the process is evident. Machine learning (ML) models proved to be valuable for automating major parts of the process, which have typically occupied the bandwidth of engineers; diverting them from adding new coverage metrics to make the designs more robust. Current research of deploying different (ML) models prove to be promising in areas such as stimulus constraining, test generation, coverage collection and bug detection and localization. An example of deploying artificial neural network (ANN) in test generation shows 24.5× speed up in functionally verifying a dual-core RISC processor specification. Another study demonstrates how k-means clustering can reduce redundancy of simulation trace dump of an AHB-to-WHISHBONE bridge by 21%, thus reducing the debugging effort by not having to inspect unnecessary waveforms. The surveyed work demonstrates a comprehensive overview of current (ML) models enhancing the functional verification process from which an insight of promising future research areas is inferred.
Freie Schlagworte:	automation of verification, functional verification, machine learning, coverage driven verification
Sachgruppe der Dewey Dezimalklassifikatin (DDC):	600 Technik, Medizin, angewandte Wissenschaften > 600 Technik 600 Technik, Medizin, angewandte Wissenschaften > 620 Ingenieurwissenschaften und Maschinenbau
Fachbereich(e)/-gebiet(e):	18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik > Integrierte Elektronische Systeme (IES)
Hinterlegungsdatum:	02 Aug 2024 12:40
Letzte Änderung:	02 Aug 2024 12:40
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• Survey on Machine Learning Algorithms Enhancing the Functional Verification Process. (deposited 29 Apr 2022 08:53)
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