Wenzel, Jakob ; Hochberger, Christian (2022)
Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis.
2022 IEEE International Workshop on Rapid System Prototyping (RSP). Shanghai, People's Republic China (13.10.2022)
doi: 10.1109/RSP57251.2022.10039003
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
Implementing nontrivial HDL designs can take a lot of time. Particularly for FPGAs, vendor tools tend to become slower, since the devices grow and thus, also the designs grow. It is therefore desirable to create mechanisms that speed up the implementation. Combining pre-implemented blocks to build the final design can be one such mechanism. It can help to reduce the time required for incremental builds, or it can reduce the time required to build families of designs. Yet, typical HDL code is not structured for this purpose. Many modules do not have the right size to be used as pre-implemented blocks. In this paper, we present a methodology to automatically analyze and modify existing HDL code such that the resulting module structure fits the purpose of pre-implementing the modules. To this end, we try to isolate parameters of the HDL code such that we have to reimplement only a small number of modules after a parameter change. The resulting tool is available as open-source software. We have tested our methodology using multiple different benchmark sets, which in total contain thousands of modules. On average, we can extract around 10% of the parameters into smaller modules.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2022 |
| Autor(en): | Wenzel, Jakob ; Hochberger, Christian |
| Art des Eintrags: | Bibliographie |
| Titel: | Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis |
| Sprache: | Englisch |
| Publikationsjahr: | 14 Oktober 2022 |
| Ort: | Shanghai, China |
| Verlag: | IEEE |
| Buchtitel: | Proceedings of the 2022 33rd International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype |
| Veranstaltungstitel: | 2022 IEEE International Workshop on Rapid System Prototyping (RSP) |
| Veranstaltungsort: | Shanghai, People's Republic China |
| Veranstaltungsdatum: | 13.10.2022 |
| DOI: | 10.1109/RSP57251.2022.10039003 |
| Kurzbeschreibung (Abstract): | Implementing nontrivial HDL designs can take a lot of time. Particularly for FPGAs, vendor tools tend to become slower, since the devices grow and thus, also the designs grow. It is therefore desirable to create mechanisms that speed up the implementation. Combining pre-implemented blocks to build the final design can be one such mechanism. It can help to reduce the time required for incremental builds, or it can reduce the time required to build families of designs. Yet, typical HDL code is not structured for this purpose. Many modules do not have the right size to be used as pre-implemented blocks. In this paper, we present a methodology to automatically analyze and modify existing HDL code such that the resulting module structure fits the purpose of pre-implementing the modules. To this end, we try to isolate parameters of the HDL code such that we have to reimplement only a small number of modules after a parameter change. The resulting tool is available as open-source software. We have tested our methodology using multiple different benchmark sets, which in total contain thousands of modules. On average, we can extract around 10% of the parameters into smaller modules. |
| Freie Schlagworte: | Codes, Conferences, Estimation, Benchmark testing, Hardware design languages, Open source software, Field programmable gate arrays |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik > Rechnersysteme |
| Hinterlegungsdatum: | 12 Apr 2024 10:15 |
| Letzte Änderung: | 12 Apr 2024 10:15 |
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