Huss, Sorin ; Stein, Oliver (2024)
A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules.
In: Journal of Low Power Electronics and Applications, 2017, 7 (1)
doi: 10.26083/tuprints-00016594
Artikel, Zweitveröffentlichung, Verlagsversion
Kurzbeschreibung (Abstract)
Over the last few decades, computer-aided engineering (CAE) tools have been developed and improved in order to ensure a short time-to-market in the chip design business. Up to now, these design tools do not yet support an integrated design strategy for the development of side-channel-resistant hardware implementations. In order to close this gap, a novel framework named AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) was developed. It supports the designer in implementing devices hardened against power attacks by exploiting novel security-driven synthesis methods. The article at hand can be seen as the second of the two contributions that address the AMASIVE framework. While the first one describes how the framework automatically detects vulnerabilities against power attacks, the second one explains how a design can be hardened in an automatic way by means of appropriate countermeasures, which are tailored to the identified weaknesses. In addition to the theoretical introduction of the fundamental concepts, we demonstrate an application to the hardening of a complete hardware implementation of the block cipher PRESENT.
| Typ des Eintrags: | Artikel |
|---|---|
| Erschienen: | 2024 |
| Autor(en): | Huss, Sorin ; Stein, Oliver |
| Art des Eintrags: | Zweitveröffentlichung |
| Titel: | A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules |
| Sprache: | Englisch |
| Publikationsjahr: | 16 Januar 2024 |
| Ort: | Darmstadt |
| Publikationsdatum der Erstveröffentlichung: | 2017 |
| Ort der Erstveröffentlichung: | Basel |
| Verlag: | MDPI |
| Titel der Zeitschrift, Zeitung oder Schriftenreihe: | Journal of Low Power Electronics and Applications |
| Jahrgang/Volume einer Zeitschrift: | 7 |
| (Heft-)Nummer: | 1 |
| Kollation: | 20 Seiten |
| DOI: | 10.26083/tuprints-00016594 |
| URL / URN: | https://tuprints.ulb.tu-darmstadt.de/16594 |
| Zugehörige Links: | |
| Herkunft: | Zweitveröffentlichung DeepGreen |
| Kurzbeschreibung (Abstract): | Over the last few decades, computer-aided engineering (CAE) tools have been developed and improved in order to ensure a short time-to-market in the chip design business. Up to now, these design tools do not yet support an integrated design strategy for the development of side-channel-resistant hardware implementations. In order to close this gap, a novel framework named AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) was developed. It supports the designer in implementing devices hardened against power attacks by exploiting novel security-driven synthesis methods. The article at hand can be seen as the second of the two contributions that address the AMASIVE framework. While the first one describes how the framework automatically detects vulnerabilities against power attacks, the second one explains how a design can be hardened in an automatic way by means of appropriate countermeasures, which are tailored to the identified weaknesses. In addition to the theoretical introduction of the fundamental concepts, we demonstrate an application to the hardening of a complete hardware implementation of the block cipher PRESENT. |
| Freie Schlagworte: | side-channel analysis, secure CAE design |
| Status: | Verlagsversion |
| URN: | urn:nbn:de:tuda-tuprints-165946 |
| Zusätzliche Informationen: | This article belongs to the Special Issue Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels |
| Sachgruppe der Dewey Dezimalklassifikatin (DDC): | 600 Technik, Medizin, angewandte Wissenschaften > 621.3 Elektrotechnik, Elektronik |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Integrierte Schaltungen und Systeme Profilbereiche Profilbereiche > Cybersicherheit (CYSEC) |
| Hinterlegungsdatum: | 16 Jan 2024 10:38 |
| Letzte Änderung: | 18 Jan 2024 14:23 |
| PPN: | |
| Zugehörige Links: | |
| Export: | |
| Suche nach Titel in: | TUfind oder in Google |
 |
Frage zum Eintrag |
Optionen (nur für Redakteure)
 |
Redaktionelle Details anzeigen |
Drucken
Impressum