Stasytis, Lukas ; István, Zsolt (2023)
Optimization Techniques for Hestenes-Jacobi SVD on FPGAs.
33rd International Conference on Field-Programmable Logic and Applications. Gothenburg, Sweden (04.09.2023-08.09.2023)
doi: 10.1109/FPL60245.2023.00028
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
Matrix decomposition, such as the Singular Value Decomposition (SVD) is an important compute-intensive task in a wide variety of fields, from radar and simulation to image processing and compression. In light of growing data sizes, accelerators, such as FPGAs, are often considered for SVD, with the goal of increasing the compute efficiency. However, to achieve high-performance computation of SVD, we need high parallelism. For that, a thorough reevaluation of the complexities involved in implementing the algorithm is necessary in light of hardware and algorithm advances. In this work, we investigate the Hestenes-Jacobi SVD (HJSVD) on FPGAs. Our findings show that the Hestenes-Jacobi method, while highly parallelizable, can become constrained in its hardware resource costs and requires careful tuning to achieve high throughput with input matrix sizes and degree of parallelism having an important effect on efficient pipelining of the architecture. We identify the key challenges in parallelizing the algorithm for modern workloads and incorporate three key optimizations: pipelining, the use of fixed-point arithmetic instead of floating-point, and the use of heterogeneous resources for vector rotations, not only DSPs.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2023 |
| Autor(en): | Stasytis, Lukas ; István, Zsolt |
| Art des Eintrags: | Bibliographie |
| Titel: | Optimization Techniques for Hestenes-Jacobi SVD on FPGAs |
| Sprache: | Englisch |
| Publikationsjahr: | 2 November 2023 |
| Verlag: | IEEE |
| Buchtitel: | Proceedings of the 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL) |
| Veranstaltungstitel: | 33rd International Conference on Field-Programmable Logic and Applications |
| Veranstaltungsort: | Gothenburg, Sweden |
| Veranstaltungsdatum: | 04.09.2023-08.09.2023 |
| DOI: | 10.1109/FPL60245.2023.00028 |
| Kurzbeschreibung (Abstract): | Matrix decomposition, such as the Singular Value Decomposition (SVD) is an important compute-intensive task in a wide variety of fields, from radar and simulation to image processing and compression. In light of growing data sizes, accelerators, such as FPGAs, are often considered for SVD, with the goal of increasing the compute efficiency. However, to achieve high-performance computation of SVD, we need high parallelism. For that, a thorough reevaluation of the complexities involved in implementing the algorithm is necessary in light of hardware and algorithm advances. In this work, we investigate the Hestenes-Jacobi SVD (HJSVD) on FPGAs. Our findings show that the Hestenes-Jacobi method, while highly parallelizable, can become constrained in its hardware resource costs and requires careful tuning to achieve high throughput with input matrix sizes and degree of parallelism having an important effect on efficient pipelining of the architecture. We identify the key challenges in parallelizing the algorithm for modern workloads and incorporate three key optimizations: pipelining, the use of fixed-point arithmetic instead of floating-point, and the use of heterogeneous resources for vector rotations, not only DSPs. |
| Fachbereich(e)/-gebiet(e): | 20 Fachbereich Informatik 20 Fachbereich Informatik > Distributed and Networked Systems |
| Hinterlegungsdatum: | 21 Nov 2023 14:32 |
| Letzte Änderung: | 21 Nov 2023 14:32 |
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