Eran, Haggai ; Zeno, Lior ; István, Zsolt ; Silberstein, Mark (2019)
Design Patterns for Code Reuse in HLS Packet Processing Pipelines.
27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019). San Diego, USA (28.04.2019-01.05.2019)
doi: 10.1109/FCCM.2019.00036
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
High-level synthesis (HLS) allows developers to be more productive in designing FPGA circuits thanks to familiar programming languages and high-level abstractions. In order to create high-performance circuits, HLS tools, such as Xilinx Vivado HLS, require following specific design patterns and techniques. Unfortunately, when applied to network packet processing tasks, these techniques limit code reuse and modularity, requiring developers to use deprecated programming conventions. We propose a methodology for developing high-speed networking applications using Vivado HLS for C++, focusing on reusability, code simplicity, and overall performance. Following this methodology, we implement a class library (ntl) with several building blocks that can be used in a wide spectrum of networking applications. We evaluate the methodology by implementing two applications: a UDP stateless firewall and a key-value store cache designed for FPGA-based SmartNICs, both processing packets at 40Gbps line-rate.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2019 |
| Autor(en): | Eran, Haggai ; Zeno, Lior ; István, Zsolt ; Silberstein, Mark |
| Art des Eintrags: | Bibliographie |
| Titel: | Design Patterns for Code Reuse in HLS Packet Processing Pipelines |
| Sprache: | Englisch |
| Publikationsjahr: | 13 Juni 2019 |
| Verlag: | IEEE |
| Buchtitel: | Proceedings: 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines |
| Veranstaltungstitel: | 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019) |
| Veranstaltungsort: | San Diego, USA |
| Veranstaltungsdatum: | 28.04.2019-01.05.2019 |
| DOI: | 10.1109/FCCM.2019.00036 |
| Kurzbeschreibung (Abstract): | High-level synthesis (HLS) allows developers to be more productive in designing FPGA circuits thanks to familiar programming languages and high-level abstractions. In order to create high-performance circuits, HLS tools, such as Xilinx Vivado HLS, require following specific design patterns and techniques. Unfortunately, when applied to network packet processing tasks, these techniques limit code reuse and modularity, requiring developers to use deprecated programming conventions. We propose a methodology for developing high-speed networking applications using Vivado HLS for C++, focusing on reusability, code simplicity, and overall performance. Following this methodology, we implement a class library (ntl) with several building blocks that can be used in a wide spectrum of networking applications. We evaluate the methodology by implementing two applications: a UDP stateless firewall and a key-value store cache designed for FPGA-based SmartNICs, both processing packets at 40Gbps line-rate. |
| Fachbereich(e)/-gebiet(e): | 20 Fachbereich Informatik 20 Fachbereich Informatik > Distributed and Networked Systems |
| Hinterlegungsdatum: | 23 Jan 2023 09:57 |
| Letzte Änderung: | 03 Apr 2023 10:41 |
| PPN: | 506540499 |
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