Assar, Adnan ; Hofmann, Klaus (2016)
A hardware implementation of the TCP protocol applying TCP-BIC and TCP-CUBIC standards.
28th International Conference on Microelectronics. Giza, Egypt (17.12.2016-20.12.2016)
doi: 10.1109/ICM.2016.7847902
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
In this paper a new hardware implementation of the TCP protocol is presented. The design can be adapted to apply either the TCP-BIC or the TCP-CUBIC standard with an input control bit. The design was done using Verilog. It was efficiently synthesized on Faraday UMC 90 nm standard-cell library. The process of synthesizing the design was iterated multiple times with different system clock frequencies to reach an optimum result. The goal of the design was to have a positive slack and the slack time should not be too small compared to the system clock period. The maximum system clock frequency achieved was 33.3 MHz and the critical path slack was 7.28 ns which comprises about 24 percent of the clock period.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2016 |
| Autor(en): | Assar, Adnan ; Hofmann, Klaus |
| Art des Eintrags: | Bibliographie |
| Titel: | A hardware implementation of the TCP protocol applying TCP-BIC and TCP-CUBIC standards |
| Sprache: | Englisch |
| Publikationsjahr: | Dezember 2016 |
| Ort: | Piscataway, NJ |
| Verlag: | IEEE |
| Buchtitel: | 2016 28th International Conference on Microelectronics (ICM) |
| Veranstaltungstitel: | 28th International Conference on Microelectronics |
| Veranstaltungsort: | Giza, Egypt |
| Veranstaltungsdatum: | 17.12.2016-20.12.2016 |
| DOI: | 10.1109/ICM.2016.7847902 |
| Kurzbeschreibung (Abstract): | In this paper a new hardware implementation of the TCP protocol is presented. The design can be adapted to apply either the TCP-BIC or the TCP-CUBIC standard with an input control bit. The design was done using Verilog. It was efficiently synthesized on Faraday UMC 90 nm standard-cell library. The process of synthesizing the design was iterated multiple times with different system clock frequencies to reach an optimum result. The goal of the design was to have a positive slack and the slack time should not be too small compared to the system clock period. The maximum system clock frequency achieved was 33.3 MHz and the critical path slack was 7.28 ns which comprises about 24 percent of the clock period. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik > Integrierte Elektronische Systeme (IES) |
| Hinterlegungsdatum: | 03 Nov 2022 10:53 |
| Letzte Änderung: | 15 Aug 2024 09:39 |
| PPN: | 505424096 |
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