Hofmann, Klaus
Hrsg.: Technische Universität Darmstadt, Integrated Electronic Systems Lab (2016)
The long way to power efficient, high performance DRAMs.
26th International Workshop on Power and Timing Modeling, Optimization and Simulation. Bremen, Germany (21.09.2016-23.09.2016)
doi: 10.1109/PATMOS.2016.7833701
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
DRAM with its simple structure of only one capacitor and one transistor is still the backbone of todays computing infrastructure especially due to its continuously decreasing costs per bit. Since most DRAM technologies still aim towards high bandwidths (bit/s) and not low latencies, it is of high importance to employ processors with sufficiently large cache structures and rely on the locality principle for software and their algorithms. The power efficiency of DRAMs has become one of the most, if not the most important design parameter, especially for server and mobile applications. With this paper the development trends towards modern, power efficient DRAM are sketched.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2016 |
| Autor(en): | Hofmann, Klaus |
| Art des Eintrags: | Bibliographie |
| Titel: | The long way to power efficient, high performance DRAMs |
| Sprache: | Deutsch |
| Publikationsjahr: | September 2016 |
| Verlag: | IEEE |
| Buchtitel: | 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) |
| Veranstaltungstitel: | 26th International Workshop on Power and Timing Modeling, Optimization and Simulation |
| Veranstaltungsort: | Bremen, Germany |
| Veranstaltungsdatum: | 21.09.2016-23.09.2016 |
| DOI: | 10.1109/PATMOS.2016.7833701 |
| Kurzbeschreibung (Abstract): | DRAM with its simple structure of only one capacitor and one transistor is still the backbone of todays computing infrastructure especially due to its continuously decreasing costs per bit. Since most DRAM technologies still aim towards high bandwidths (bit/s) and not low latencies, it is of high importance to employ processors with sufficiently large cache structures and rely on the locality principle for software and their algorithms. The power efficiency of DRAMs has become one of the most, if not the most important design parameter, especially for server and mobile applications. With this paper the development trends towards modern, power efficient DRAM are sketched. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik > Integrierte Elektronische Systeme (IES) |
| Hinterlegungsdatum: | 03 Nov 2022 10:47 |
| Letzte Änderung: | 15 Aug 2024 09:39 |
| PPN: | 505181215 |
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