Belda, Nadew Adisu (2021)
HVDC Circuit Breakers -- Test Requirements, Methods and Circuits.
Technische Universität Darmstadt
doi: 10.26083/tuprints-00019722
Dissertation, Erstveröffentlichung, Verlagsversion
Kurzbeschreibung (Abstract)
Recently, several industrial concepts of high-voltage direct current (HVDC) circuit breakers (CBs) have been developed into prototypes, and few have been installed in service. However, due to a lack of operational experience, there exist no clearly defined requirements that the HVDC CBs should satisfy. This thesis focuses on defining test requirements and developing a test method capable of verifying the rated fault current breaking performance of the HVDC CBs. First, detailed simulation studies of fault currents in a conceptual multi-terminal HVDC (MTDC) grid is conducted. The sequence of events and the temporal stages of fault current development following the occurrence of a fault are identified. Second, the stresses on an HVDC CB during a fault current interruption process are identified. It is found that an HVDC CB is subjected to not only DC current and voltage but also energy stress. Third, various test methods and circuits used for testing HVDC CBs are investigated, and the performance of each test circuit is evaluated against the stresses identified from the simulation of the MTDC grid. A novel method of testing an HVDC CB using AC short-circuit generator operated at low power frequency is proposed, and its performance is demonstrated in a test laboratory. Fourth, a complete test circuit based on the proposed method is designed and implemented using existing infrastructure at a high-power test facility. Pragmatic solutions to address some of the inherent challenges are proposed and experimentally verified. Tests validating the proposed method and circuit have been conducted on several prototypes of HVDC CBs supplied by original equipment manufacturers (OEMs) and the adequacy of the test method and circuit is evaluated and verified from the test results. Fifth, in order to justify the defined test requirements, an experimental investigation of the stresses on the internal components of an HVDC CB, namely, the vacuum interrupter (VI) and the metal oxide surge arrester (MOSA), is performed. It is found that different designs of VIs exhibit different performance. Furthermore, the test results justify the importance of defining not only the high-current interruptions but also the low-current interruptions as part of the test requirements. In addition, the criticality of ensuring sufficient duration of TIV during the fault current breaking is verified. Also, it is found that a well designed MOSA branch including the proper choice of MO varistors and adequately matched columns is crucial for the reliable performance of the HVDC CB.
Typ des Eintrags: | Dissertation | ||||
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Erschienen: | 2021 | ||||
Autor(en): | Belda, Nadew Adisu | ||||
Art des Eintrags: | Erstveröffentlichung | ||||
Titel: | HVDC Circuit Breakers -- Test Requirements, Methods and Circuits | ||||
Sprache: | Englisch | ||||
Referenten: | Hinrichsen, Prof. Dr Volker ; Smeets, Prof. Dr. Rene | ||||
Publikationsjahr: | 2021 | ||||
Ort: | Darmstadt | ||||
Kollation: | xiii, 227 Seiten | ||||
Datum der mündlichen Prüfung: | 22 September 2021 | ||||
DOI: | 10.26083/tuprints-00019722 | ||||
URL / URN: | https://tuprints.ulb.tu-darmstadt.de/19722 | ||||
Kurzbeschreibung (Abstract): | Recently, several industrial concepts of high-voltage direct current (HVDC) circuit breakers (CBs) have been developed into prototypes, and few have been installed in service. However, due to a lack of operational experience, there exist no clearly defined requirements that the HVDC CBs should satisfy. This thesis focuses on defining test requirements and developing a test method capable of verifying the rated fault current breaking performance of the HVDC CBs. First, detailed simulation studies of fault currents in a conceptual multi-terminal HVDC (MTDC) grid is conducted. The sequence of events and the temporal stages of fault current development following the occurrence of a fault are identified. Second, the stresses on an HVDC CB during a fault current interruption process are identified. It is found that an HVDC CB is subjected to not only DC current and voltage but also energy stress. Third, various test methods and circuits used for testing HVDC CBs are investigated, and the performance of each test circuit is evaluated against the stresses identified from the simulation of the MTDC grid. A novel method of testing an HVDC CB using AC short-circuit generator operated at low power frequency is proposed, and its performance is demonstrated in a test laboratory. Fourth, a complete test circuit based on the proposed method is designed and implemented using existing infrastructure at a high-power test facility. Pragmatic solutions to address some of the inherent challenges are proposed and experimentally verified. Tests validating the proposed method and circuit have been conducted on several prototypes of HVDC CBs supplied by original equipment manufacturers (OEMs) and the adequacy of the test method and circuit is evaluated and verified from the test results. Fifth, in order to justify the defined test requirements, an experimental investigation of the stresses on the internal components of an HVDC CB, namely, the vacuum interrupter (VI) and the metal oxide surge arrester (MOSA), is performed. It is found that different designs of VIs exhibit different performance. Furthermore, the test results justify the importance of defining not only the high-current interruptions but also the low-current interruptions as part of the test requirements. In addition, the criticality of ensuring sufficient duration of TIV during the fault current breaking is verified. Also, it is found that a well designed MOSA branch including the proper choice of MO varistors and adequately matched columns is crucial for the reliable performance of the HVDC CB. |
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Alternatives oder übersetztes Abstract: |
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Status: | Verlagsversion | ||||
URN: | urn:nbn:de:tuda-tuprints-197229 | ||||
Sachgruppe der Dewey Dezimalklassifikatin (DDC): | 600 Technik, Medizin, angewandte Wissenschaften > 600 Technik 600 Technik, Medizin, angewandte Wissenschaften > 620 Ingenieurwissenschaften und Maschinenbau |
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Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Elektrische Energiesysteme > Hochspannungstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Elektrische Energiesysteme |
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Hinterlegungsdatum: | 11 Okt 2021 12:07 | ||||
Letzte Änderung: | 12 Okt 2021 05:32 | ||||
PPN: | |||||
Referenten: | Hinrichsen, Prof. Dr Volker ; Smeets, Prof. Dr. Rene | ||||
Datum der mündlichen Prüfung / Verteidigung / mdl. Prüfung: | 22 September 2021 | ||||
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