Schwarz, Alexander ; Hochberger, Christian
Hrsg.: Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo (2021)
Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode.
34th International Conference on Architecture of Computing Systems. virtual Conference (07.07.2021-08.07.2021)
doi: 10.1007/978-3-030-81682-7_7
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
Java Bytecode is used as binary format for a number of programming languages and programming systems. Since Java virtual machines exist for many platforms, it can be regarded as a universal execution format. Consequently, several hardware implementations of Bytecode processors exist. Unfortunately, they all suffer from the inefficiencies of the Bytecode principle. Particularly, the operand stack and the local variable storage are bottlenecks during execution. In this contribution, we evaluate the performance gain that can be achieved by replacing Bytecode with a data flow oriented instruction set architecture (ISA). We describe the changes that are necessary to adapt an existing Bytecode processor to the new ISA. Ultimately, we compare execution times and HW resources for both processors, which are based on identical ALUs and heap memory model. Execution times are evaluated using the SPEC JVM98 benchmark and a set of micro benchmarks which have a very flat call graph. SPEC JVM98 reaches a speedup of 1.76 and the micro benchmarks even gain a factor of 2.80.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2021 |
| Herausgeber: | Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo |
| Autor(en): | Schwarz, Alexander ; Hochberger, Christian |
| Art des Eintrags: | Bibliographie |
| Titel: | Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode |
| Sprache: | Englisch |
| Publikationsjahr: | 15 Juli 2021 |
| Verlag: | Springer |
| Buchtitel: | Architecture of Computing Systems |
| Reihe: | Lecture Notes in Computer Science |
| Band einer Reihe: | 12800 |
| Veranstaltungstitel: | 34th International Conference on Architecture of Computing Systems |
| Veranstaltungsort: | virtual Conference |
| Veranstaltungsdatum: | 07.07.2021-08.07.2021 |
| DOI: | 10.1007/978-3-030-81682-7_7 |
| Kurzbeschreibung (Abstract): | Java Bytecode is used as binary format for a number of programming languages and programming systems. Since Java virtual machines exist for many platforms, it can be regarded as a universal execution format. Consequently, several hardware implementations of Bytecode processors exist. Unfortunately, they all suffer from the inefficiencies of the Bytecode principle. Particularly, the operand stack and the local variable storage are bottlenecks during execution. In this contribution, we evaluate the performance gain that can be achieved by replacing Bytecode with a data flow oriented instruction set architecture (ISA). We describe the changes that are necessary to adapt an existing Bytecode processor to the new ISA. Ultimately, we compare execution times and HW resources for both processors, which are based on identical ALUs and heap memory model. Execution times are evaluated using the SPEC JVM98 benchmark and a set of micro benchmarks which have a very flat call graph. SPEC JVM98 reaches a speedup of 1.76 and the micro benchmarks even gain a factor of 2.80. |
| Fachbereich(e)/-gebiet(e): | 18 Fachbereich Elektrotechnik und Informationstechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik 18 Fachbereich Elektrotechnik und Informationstechnik > Institut für Datentechnik > Rechnersysteme |
| Hinterlegungsdatum: | 09 Aug 2021 07:16 |
| Letzte Änderung: | 09 Aug 2021 07:16 |
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