Hirmer, Katrin (2019)
Interference-Aware Integration of Mixed-Signal Designs and Ultra High Voltage Pulse Generators for System-on-Chips.
Technische Universität Darmstadt
Dissertation, Erstveröffentlichung

Kurzbeschreibung (Abstract)

The interference-aware implementation of system-on-chips (SoCs) including ultra high voltage pulse generators and mixed-signal devices, which are for example used in rectifiers or gate drivers, enables the continuous miniaturization of system electronics. Square wave signals with high amplitudes and slew rates can interfere significantly with monolithically integrated low voltage electronics. The prediction of these interferences on SoCs prior to fabrication is essential to take countermeasures. This helps to ensure the functionality of the system and reduces development costs. The main objective of this work is to develop a model which can predict the influences of high voltage pulses on circuits with low supply voltages by simulations. The integration of this model into the conventional design flow of integrated circuits enables SPICE simulations without any additional license fees. The investigations within this thesis allow deriving recommendations for the integration of high voltage pulses and low voltage circuitry within a SoC. Two SoCs have been fabricated in a silicon-on-insulator process. These can be used to emit light from an electroluminescent device as well as driving a capacitive sensor at the same time. The implemented ultra high voltage pulse generator can deliver pulses with up to ±300 V at slew rates of up to 99.56 V/µs. It is able to drive capacitive loads of 10 nF at frequencies of up to 5 kHz. At the same time, a spread spectrum clock generator (SSCG) with a resolution of 9 bit can excite the capacitive sensor with a bandwidth of 10.14 MHz and an attenuation of 33.17 dB with a 5 V power supply. During the switching operation of the ultra high voltage pulse generator, deviations of the operating frequency of the SSCG can be observed. These can mostly be explained by substrate coupling. To verify the coupling mechanism, on the one hand, relevant impedances of the substrate network are measured and compared to calculated values within this thesis. On the other hand, the coupling of the high voltage pulse generator to the substrate as well as the influences of variations of the substrate potential on low voltage designs are recorded by measurement. To predict the interferences on mixed-signal devices, a substrate netlist can be extracted with the help of the SoC layout. The parameters of the components within the substrate equivalent circuit can be analytically calculated by using geometric dimensions extracted from the layout of the SoC. The substrate netlist can be simulated along with the post-layout of the integrated components. The modeling of the supply voltage as well as the packaging is of great importance for the simulation. The investigations of this thesis result in recommendations for the implementation of SoCs with ultra high voltage pulse generators and mixed-signal devices. They include considerations for the circuit implementation, the layout as well as the package selection. For the fabricated SoCs, the frequency change of the SSCG can be reduced by 77.35 %.

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