Bieger, Jens ; Huss, Sorin ; Jung, Michael ; Klaus, Stephan ; Steininger, Thomas (2004)
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach.
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application and limitations of the architecture. In a top-down approach a real-time MPEG 1 Layer 3 (MP3) decoder is designed on this SoC, which integrates FPGA resources and an AVR microcontroller core within a single chip. An intensive design space exploration based on simulations on different levels of abstractions is fundamental for a real-time implementation on this limited architecture. After determining a suited functional partitioning a special DSP is implemented on the FPGA, wherefore an instruction set simulator is build, which allows concurrent HW/SW development.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2004 |
| Autor(en): | Bieger, Jens ; Huss, Sorin ; Jung, Michael ; Klaus, Stephan ; Steininger, Thomas |
| Art des Eintrags: | Bibliographie |
| Titel: | Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach |
| Sprache: | Englisch |
| Publikationsjahr: | Januar 2004 |
| Buchtitel: | Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004) with the 3rd International Conference on Embedded Systems |
| Kurzbeschreibung (Abstract): | The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application and limitations of the architecture. In a top-down approach a real-time MPEG 1 Layer 3 (MP3) decoder is designed on this SoC, which integrates FPGA resources and an AVR microcontroller core within a single chip. An intensive design space exploration based on simulations on different levels of abstractions is fundamental for a real-time implementation on this limited architecture. After determining a suited functional partitioning a special DSP is implemented on the FPGA, wherefore an instruction set simulator is build, which allows concurrent HW/SW development. |
| Fachbereich(e)/-gebiet(e): | 20 Fachbereich Informatik 20 Fachbereich Informatik > Integrierte Schaltungen und Systeme |
| Hinterlegungsdatum: | 31 Dez 2016 00:15 |
| Letzte Änderung: | 07 Dez 2018 12:24 |
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