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A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications

Laue, Ralf and Molter, Gregor and Rieder, Felix and Saxena, Kartik and Huss, Sorin (2008):
A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications.
In: IEEE Computer Society Annual Symposium on VLSI, DOI: 10.1109/ISVLSI.2008.9,
[Conference or Workshop Item]

Abstract

We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.

Item Type: Conference or Workshop Item
Erschienen: 2008
Creators: Laue, Ralf and Molter, Gregor and Rieder, Felix and Saxena, Kartik and Huss, Sorin
Title: A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications
Language: ["languages_typename_1" not defined]
Abstract:

We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.

Title of Book: IEEE Computer Society Annual Symposium on VLSI
Uncontrolled Keywords: Public Key Cryptography, Multi-Core, Parallelization
Divisions: 20 Department of Computer Science > Integrated Circuits and Systems
20 Department of Computer Science
Date Deposited: 31 Dec 2016 00:15
DOI: 10.1109/ISVLSI.2008.9
Identification Number: ISS:Laue:2008:ANovelMultip:106
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