Laue, Ralf ; Molter, Gregor ; Rieder, Felix ; Saxena, Kartik ; Huss, Sorin (2008)
A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications.
doi: 10.1109/ISVLSI.2008.9
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2008 |
| Autor(en): | Laue, Ralf ; Molter, Gregor ; Rieder, Felix ; Saxena, Kartik ; Huss, Sorin |
| Art des Eintrags: | Bibliographie |
| Titel: | A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications |
| Sprache: | Englisch |
| Publikationsjahr: | April 2008 |
| Buchtitel: | IEEE Computer Society Annual Symposium on VLSI |
| DOI: | 10.1109/ISVLSI.2008.9 |
| Kurzbeschreibung (Abstract): | We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels. |
| Freie Schlagworte: | Public Key Cryptography, Multi-Core, Parallelization |
| Fachbereich(e)/-gebiet(e): | 20 Fachbereich Informatik > Integrierte Schaltungen und Systeme 20 Fachbereich Informatik |
| Hinterlegungsdatum: | 31 Dez 2016 00:15 |
| Letzte Änderung: | 17 Mai 2018 08:56 |
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