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A Stochastic Method for Security Evaluation of Cryptographic FPGA Implementations

Kasper, Michael and Schindler, Werner and Stoettinger, Marc (2010):
A Stochastic Method for Security Evaluation of Cryptographic FPGA Implementations.
In: Proceedings of the 2010 International Conference on Field-Programmable Technology - FPT 2010, [Conference or Workshop Item]

Abstract

We introduce a stochastic method for the security evaluation and dynamic power consumption analysis in the context of side-channel analysis. This method allows to estimate data-dependent power consumption induced by secret parameters, e.g. a cryptographic key, which may be exploited in power attacks. In particular, IP-cores for security applications on FPGAs have to be made secure against these attacks. We show that the same stochastic methods provide FPGA designers constructive feedback on the information leakage of the design. Applied as a constructive tool these stochastic methods allow the designer to quantify the side-channel resistance and weaknesses of the IP-core design, a feature which supports the design of secure and side-channel resistant implementations, especially on FPGAs.

Item Type: Conference or Workshop Item
Erschienen: 2010
Creators: Kasper, Michael and Schindler, Werner and Stoettinger, Marc
Title: A Stochastic Method for Security Evaluation of Cryptographic FPGA Implementations
Language: ["languages_typename_1" not defined]
Abstract:

We introduce a stochastic method for the security evaluation and dynamic power consumption analysis in the context of side-channel analysis. This method allows to estimate data-dependent power consumption induced by secret parameters, e.g. a cryptographic key, which may be exploited in power attacks. In particular, IP-cores for security applications on FPGAs have to be made secure against these attacks. We show that the same stochastic methods provide FPGA designers constructive feedback on the information leakage of the design. Applied as a constructive tool these stochastic methods allow the designer to quantify the side-channel resistance and weaknesses of the IP-core design, a feature which supports the design of secure and side-channel resistant implementations, especially on FPGAs.

Title of Book: Proceedings of the 2010 International Conference on Field-Programmable Technology - FPT 2010
Uncontrolled Keywords: Secure Things;CASCADE;power analysis, stochastic approach, secure design, constructive side-channel analysis
Divisions: LOEWE > LOEWE-Zentren > CASED – Center for Advanced Security Research Darmstadt
LOEWE > LOEWE-Zentren
LOEWE
Date Deposited: 31 Dec 2016 00:15
Identification Number: ISS:Kasper:2010:AStochasticM:191
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