Kasper, Michael ; Schindler, Werner ; Stoettinger, Marc (2010)
A Stochastic Method for Security Evaluation of Cryptographic FPGA Implementations.
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
We introduce a stochastic method for the security evaluation and dynamic power consumption analysis in the context of side-channel analysis. This method allows to estimate data-dependent power consumption induced by secret parameters, e.g. a cryptographic key, which may be exploited in power attacks. In particular, IP-cores for security applications on FPGAs have to be made secure against these attacks. We show that the same stochastic methods provide FPGA designers constructive feedback on the information leakage of the design. Applied as a constructive tool these stochastic methods allow the designer to quantify the side-channel resistance and weaknesses of the IP-core design, a feature which supports the design of secure and side-channel resistant implementations, especially on FPGAs.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2010 |
| Autor(en): | Kasper, Michael ; Schindler, Werner ; Stoettinger, Marc |
| Art des Eintrags: | Bibliographie |
| Titel: | A Stochastic Method for Security Evaluation of Cryptographic FPGA Implementations |
| Sprache: | Englisch |
| Publikationsjahr: | Dezember 2010 |
| Buchtitel: | Proceedings of the 2010 International Conference on Field-Programmable Technology - FPT 2010 |
| Kurzbeschreibung (Abstract): | We introduce a stochastic method for the security evaluation and dynamic power consumption analysis in the context of side-channel analysis. This method allows to estimate data-dependent power consumption induced by secret parameters, e.g. a cryptographic key, which may be exploited in power attacks. In particular, IP-cores for security applications on FPGAs have to be made secure against these attacks. We show that the same stochastic methods provide FPGA designers constructive feedback on the information leakage of the design. Applied as a constructive tool these stochastic methods allow the designer to quantify the side-channel resistance and weaknesses of the IP-core design, a feature which supports the design of secure and side-channel resistant implementations, especially on FPGAs. |
| Freie Schlagworte: | Secure Things;CASCADE;power analysis, stochastic approach, secure design, constructive side-channel analysis |
| Fachbereich(e)/-gebiet(e): | LOEWE > LOEWE-Zentren > CASED – Center for Advanced Security Research Darmstadt LOEWE > LOEWE-Zentren LOEWE |
| Hinterlegungsdatum: | 31 Dez 2016 00:15 |
| Letzte Änderung: | 17 Mai 2018 13:02 |
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