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A Novel Cryptoprocessor Architecture for Chained Merkle Signature Scheme

Shoufan, Abdulhadi and Huber, Nico and Molter, Gregor (2011):
A Novel Cryptoprocessor Architecture for Chained Merkle Signature Scheme.
In: Microprocessors and Microsystems, Embedded Hardware Design, Elsevier, 35.pp. 34-47, DOI: 10.1016/j.micpro.2010.07.002,
[Article]

Abstract

One-time signature schemes rely on hash functions and are, therefore, assumed to be resistant to attacks by quantum computers. These approaches inherently raise a key management problem, as the key pair can be used only for one message. That means, for one-time signature schemes to work, the sender must deliver the veri�cation key together with the message and the signature. Upon reception, the receiver has to verify the authenticity of the veri�cation key before verifying the signature itself. Hash-tree based solutions tackle this problem by basing the authenticity of a large number of veri�cation keys on the authenticity of a root key. This approach, however, causes computation, communication, and storage overhead. Due to hardware acceleration, this paper proposes, for the �rst time, a processor architecture which boosts the performance of a one-time signature scheme without degrading memory usage and communication properties...

Item Type: Article
Erschienen: 2011
Creators: Shoufan, Abdulhadi and Huber, Nico and Molter, Gregor
Title: A Novel Cryptoprocessor Architecture for Chained Merkle Signature Scheme
Language: ["languages_typename_1" not defined]
Abstract:

One-time signature schemes rely on hash functions and are, therefore, assumed to be resistant to attacks by quantum computers. These approaches inherently raise a key management problem, as the key pair can be used only for one message. That means, for one-time signature schemes to work, the sender must deliver the veri�cation key together with the message and the signature. Upon reception, the receiver has to verify the authenticity of the veri�cation key before verifying the signature itself. Hash-tree based solutions tackle this problem by basing the authenticity of a large number of veri�cation keys on the authenticity of a root key. This approach, however, causes computation, communication, and storage overhead. Due to hardware acceleration, this paper proposes, for the �rst time, a processor architecture which boosts the performance of a one-time signature scheme without degrading memory usage and communication properties...

Journal or Publication Title: Microprocessors and Microsystems, Embedded Hardware Design, Elsevier
Volume: 35.
Uncontrolled Keywords: Secure Things;chained merkle signature scheme, cryptography hardware and implementation, cryptoprocessor, fpga, winternitz one-time signature
Divisions: LOEWE > LOEWE-Zentren > CASED – Center for Advanced Security Research Darmstadt
LOEWE > LOEWE-Zentren
LOEWE
Date Deposited: 31 Dec 2016 00:15
DOI: 10.1016/j.micpro.2010.07.002
Identification Number: ISS:Shoufan:2011:ANovelCrypto:187
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