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Number of items: 6.

Hinkelmann, Heiko ; Murgan, T. ; Liu, G. ; Zipf, Peter ; Glesner, Manfred (2007):
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
In: International Workshop on Reconfigurable Communication-centric System-on-Chips (ReCoSoC), Montpellier, France 2007, [Conference or Workshop Item]

Glesner, Manfred ; Murgan, T. ; Hollstein, T. ; Zipf, Peter ; Soffke, O. ; Hinkelmann, Heiko (2007):
System Design Challenges in the Nanoscale Era.
In: Scientific Bulletin of the Faculty of Electronics, Telecommunications and Informatics, Gdansk Univ. of Technology - Information Technology Series, volume 12, pages 3-14, 2007., [Article]

Pandey, S. ; Murgan, T. ; Glesner, Manfred (2006):
Energy Conscious Simultaneous Voltage Scaling and On-Chip Communication Bus Synthesis.
In: VLSI-SoC: Research Trends in VLSI and Systems on Chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France / Hrsg. Giovanni DeMicheli; Hrsg. Salvador Mir; Hrsg. Ricardo R, 1. Ed. - Berlin, Springer US, [Conference or Workshop Item]

Murgan, T. ; Momeni, M. ; Ortiz, A. G. ; Glesner, Manfred (2006):
A High-Level Compact Pattern-Dependent Delay Model for High-Speed Point -to-Point Interconncects.
In: Proceedings of the 2006 International Conferenceon Computer-Aided Design, pp. 323-328,
IEEE, IEEE/ACM International Conference on Computer Aided Design (ICCAD-2006), San Jose, USA, 05.-09.11.2006, ISSN 1092-3152,
DOI: 10.1109/ICCAD.2006.320053,
[Conference or Workshop Item]

Murgan, T. ; Bacinschi, P. B. ; Ortiz, A. G. ; Glesner, Manfred (2006):
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-Wire Capacitance.
In: Integrated circuit and system design : power and timing modeling, optimization and simulation, pp. 169-180,
Springer, 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier, France, 13.-15.09.2006, ISBN 978-3-540-39094-7,
DOI: 10.1007/11847083_17,
[Conference or Workshop Item]

Murgan, T. ; Mitea, O. ; Pandey, S. ; Bacinschi, P. B. ; Glesner, Manfred (2006):
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
In: IFIP VLSI-SoC 2006 : IFIP WG 10.5 International Conference on Very Large Scale Integration System-on-Chip ; Nice, France, October 16 - 18, 2006 / sponsored by IFIP WG 10.5 ... Organised by TIMA Laboratory, Grenoble, France. [Ed. by Salvador Mir ...]. - Ge, Genoble, TIMA Laboratory, [Conference or Workshop Item]

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