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Number of items: 9.

Schneider, T. ; Mades, J. ; Windisch, A. ; Hollstein, T. ; Glesner, M. ; Kruse, T. (2001):
Eine WEB-basierte Simulationsumgebung für VHDL-AMS.
In: E.I.S. 2001: ITG/GI/GMM-Workshop Entwurf Integrierter Schaltungen <10, 2001, Dresden>; Tagungsbd. S. 273 - 276, [Conference or Workshop Item]

Sporer, Mathias ; Windisch, A. ; Ziegler, E. ; Monjau, D. ; Schneider, T. ; Mades, J. ; Grimm, C. ; Oehler, P. (2001):
RODOS - Reuse oriented design of embedded systems.
In: Demonstrations at the University Booth of the DATE Conference <2001, München>: Proceedings. - Tübingen: Wilhelm-Schickard-Inst. für Informatik, 2001. S. 14, Tübingen, Wilhelm-Schickard-Inst. für Informatik, [Conference or Workshop Item]

Windisch, A. ; Monjau, D. ; Schneider, T. ; Mades, J. ; Glesner, M. ; Ecker, W. (2001):
A VHDL-Centric mixed language simulation environment.
In: System-on-chip-methodologies and design languages. Hrsg.: P. J. Ashenden. - Boston, Mass.: Kluwer Acad. Publ., 2001. S. 37 - 46, Boston, Mass., Kluwer Acad. Publ., [Book Section]

Ecker, Wolfgang ; Heuchling, M. ; Mades, J. ; Schneider, C. ; Schneider, T. ; Windisch, A. ; Yang, K. ; Zambaldi, M. (1999):
VHDL2HYPER: a highly flexible hypertext generator for VHDL models.
In: VIUF : Verilog-HDL International Users Forum <1999, Orlando, Fla.>; Fall Workshop ; Proceedings, [Conference or Workshop Item]

Windisch, A. ; Ecker, W. ; Hammer, C. ; Mades, J. ; Schneider, T. ; Yang, K. (1999):
An adaptable VHDL-AMS compiler front-end.
In: Forum of Design Languages <1999, Lyon>: Proceedings, [Conference or Workshop Item]

Ecker, Wolfgang ; Mades, J. ; Schneider, T. ; Windisch, A. ; Yang, K. (1999):
A dependency graph for VHDL design files and design units and its application in a VHDL design environment.
In: International HDL Conference and Exhibition <1999, Santa Clara, USA>: Proceedings, [Conference or Workshop Item]

Ecker, Wolfgang ; Glesner, M. ; Hollstein, T. ; Mades, J. ; Schneider, T. ; Theisen, M. ; Windisch, A. ; Yang, K. (1999):
A flexible connected data system for VHDL source code analysis, transformation and processing.
In: Entwurf Integrierter Schaltungen <9, 1999, Darmstadt>. Vol. 1. S. 209-216. - Berlin: VDE-Verl., 1999, Berlin, VDE-Verl., [Conference or Workshop Item]

Ecker, Wolfgang ; Mades, J. ; Schneider, T. ; Windisch, A. ; Yang, K. (1999):
A makefile generator for VHDL models under consideration of hierarchical names, identifier-visibility and identifier-hiding.
In: Forum of Design Languages <1999, Lyon>: Proceedings, [Conference or Workshop Item]

Ecker, Wolfgang ; Mades, J. ; Schneider, T. ; Windisch, A. ; Yang, K. (1999):
A scalable multithreaded compiler front-end.
In: Conference on Parallel Computing <1999, Delft, NL>: Proceedings, [Conference or Workshop Item]

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