Meister, Gerd (1996)
Evaluation of parallel logic simulation using DVSIM.
Conference or Workshop Item, Bibliographie
| Item Type: | Conference or Workshop Item |
|---|---|
| Erschienen: | 1996 |
| Creators: | Meister, Gerd |
| Type of entry: | Bibliographie |
| Title: | Evaluation of parallel logic simulation using DVSIM |
| Language: | English |
| Date: | 1996 |
| Series: | Hawaii International Conference on System Sciences <29, 1996, Hawaii>: Proceedings. S. 397-406 |
| Divisions: | 20 Department of Computer Science |
| Date Deposited: | 19 Nov 2008 16:02 |
| Last Modified: | 26 Aug 2018 21:21 |
| PPN: | |
| Export: | |
| Suche nach Titel in: | TUfind oder in Google |
 |
Send an inquiry |
Options (only for editors)
 |
Show editorial Details |
Drucken
Impressum