Meister, Gerd (1996):
Evaluation of parallel logic simulation using DVSIM.
In: Hawaii International Conference on System Sciences <29, 1996, Hawaii>: Proceedings. S. 397-406, [Conference or Workshop Item]
| Item Type: | Conference or Workshop Item |
|---|---|
| Erschienen: | 1996 |
| Creators: | Meister, Gerd |
| Title: | Evaluation of parallel logic simulation using DVSIM |
| Language: | English |
| Series: | Hawaii International Conference on System Sciences <29, 1996, Hawaii>: Proceedings. S. 397-406 |
| Divisions: | 20 Department of Computer Science |
| Date Deposited: | 19 Nov 2008 16:00 |
| License: | [undefiniert] |
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