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Regularization of hierarchical VHDL-AMS models using bipartite graphs

Mades, Jochen ; Glesner, Manfred (2002):
Regularization of hierarchical VHDL-AMS models using bipartite graphs.
In: Design Automation Conference <Association for Computing Machinery, 39, 2002, New Orleans, La.>: DAC 2002, proceedings.- New York, NY: ACM Order Dept., 2002.- ISBN 1-583-13538-6.- CD-ROM, New York, NY, ACM Order Dept., [Conference or Workshop Item]

Item Type: Conference or Workshop Item
Erschienen: 2002
Creators: Mades, Jochen ; Glesner, Manfred
Title: Regularization of hierarchical VHDL-AMS models using bipartite graphs
Language: English
Series Name: Design Automation Conference <Association for Computing Machinery, 39, 2002, New Orleans, La.>: DAC 2002, proceedings.- New York, NY: ACM Order Dept., 2002.- ISBN 1-583-13538-6.- CD-ROM
Place of Publication: New York, NY
Publisher: ACM Order Dept.
Divisions: 18 Department of Electrical Engineering and Information Technology
Date Deposited: 20 Nov 2008 08:15
License: [undefiniert]
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