Heuschkel, Jens ; Thomasberger, Philipp ; Gedeon, Julien ; Mühlhäuser, Max (2019)
VirtualStack: Green High Performance Network Protocol Processing Leveraging FPGAs.
2019 IEEE Global Communications Conference: Green Communication Systems and Networks (Globecom2019 GCSN). Waikoloa, USA (09.12.2019-13.12.2019)
Conference or Workshop Item, Bibliographie
Abstract
In times of cloud services and IoT, network protocol processing is a big part of the CPU utilization today. Foong et al. proposed the rule of thumb for TCP, that a single-core CPU needs about 1 Hz clock frequency to produce 1 bit/s worth of TCP data packets. Unfortunately, CPU speed has stagnated around 5 GHz in recent years resulting in a upper limit of 5 GBit/s throughput with single-threaded network processing. Further, CPU featuring such high clock rates (e.g., Intel Core i7-8086K) have rated TDP around 95 W, resulting in very high power consumption for high throughput situations. Meanwhile, industry offers some hardware acceleration for TCP as part of their server network cards, to relief the server CPUs and increase the energy efficiency. However this is just a small support as state and management still needs the CPU of the host system. In this paper, we present an approach based on field programmable gate arrays (FPGA) to not only free up CPU cycles but provide a scaleable and energy efficient concept to fully utilize high-speed network interfaces, whereby maintaining the flexibility of software solutions. For our evaluation, we utilized the NetFPGA Sume, proofing to achieve the linerate of connected SFP+ ports while power consumption stays below 6 W. By leveraging the network protocol virtualization, the hardware acceleration approach is not only deploy-able but stays flexible enough to adapt new networking paradigms quickly.
Item Type: | Conference or Workshop Item |
---|---|
Erschienen: | 2019 |
Creators: | Heuschkel, Jens ; Thomasberger, Philipp ; Gedeon, Julien ; Mühlhäuser, Max |
Type of entry: | Bibliographie |
Title: | VirtualStack: Green High Performance Network Protocol Processing Leveraging FPGAs |
Language: | English |
Date: | December 2019 |
Place of Publication: | Waikoloa, USA |
Event Title: | 2019 IEEE Global Communications Conference: Green Communication Systems and Networks (Globecom2019 GCSN) |
Event Location: | Waikoloa, USA |
Event Dates: | 09.12.2019-13.12.2019 |
Abstract: | In times of cloud services and IoT, network protocol processing is a big part of the CPU utilization today. Foong et al. proposed the rule of thumb for TCP, that a single-core CPU needs about 1 Hz clock frequency to produce 1 bit/s worth of TCP data packets. Unfortunately, CPU speed has stagnated around 5 GHz in recent years resulting in a upper limit of 5 GBit/s throughput with single-threaded network processing. Further, CPU featuring such high clock rates (e.g., Intel Core i7-8086K) have rated TDP around 95 W, resulting in very high power consumption for high throughput situations. Meanwhile, industry offers some hardware acceleration for TCP as part of their server network cards, to relief the server CPUs and increase the energy efficiency. However this is just a small support as state and management still needs the CPU of the host system. In this paper, we present an approach based on field programmable gate arrays (FPGA) to not only free up CPU cycles but provide a scaleable and energy efficient concept to fully utilize high-speed network interfaces, whereby maintaining the flexibility of software solutions. For our evaluation, we utilized the NetFPGA Sume, proofing to achieve the linerate of connected SFP+ ports while power consumption stays below 6 W. By leveraging the network protocol virtualization, the hardware acceleration approach is not only deploy-able but stays flexible enough to adapt new networking paradigms quickly. |
Uncontrolled Keywords: | protocol virtualization; FPGA acceleration; energy efficiency |
Divisions: | 20 Department of Computer Science 20 Department of Computer Science > Telecooperation DFG-Collaborative Research Centres (incl. Transregio) DFG-Collaborative Research Centres (incl. Transregio) > Collaborative Research Centres DFG-Collaborative Research Centres (incl. Transregio) > Collaborative Research Centres > CRC 1053: MAKI – Multi-Mechanisms Adaptation for the Future Internet DFG-Collaborative Research Centres (incl. Transregio) > Collaborative Research Centres > CRC 1053: MAKI – Multi-Mechanisms Adaptation for the Future Internet > B: Adaptation Mechanisms DFG-Collaborative Research Centres (incl. Transregio) > Collaborative Research Centres > CRC 1053: MAKI – Multi-Mechanisms Adaptation for the Future Internet > B: Adaptation Mechanisms > Subproject B2: Coordination and Execution |
Date Deposited: | 22 Jul 2019 07:18 |
Last Modified: | 14 Jun 2021 06:14 |
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