Li, Changgong (2019)
Implementation of an AMIDAR-based Java Processor.
Technische Universität Darmstadt
Ph.D. Thesis, Primary publication
Abstract
This thesis presents a Java processor based on the Adaptive Microinstruction Driven Architecture (AMIDAR). This processor is intended as a research platform for investigating adaptive processor architectures. Combined with a configurable accelerator, it is able to detect and speed up hot spots of arbitrary applications dynamically. In contrast to classical RISC processors, an AMIDAR-based processor consists of four main types of components: a token machine, functional units (FUs), a token distribution network and an FU interconnect structure. The token machine is a specialized functional unit and controls the other FUs by means of tokens. These tokens are delivered to the FUs over the token distribution network. The tokens inform the FUs about what to do with input data and where to send the results. Data is exchanged among the FUs over the FU interconnect structure. Based on the virtual machine architecture defined by the Java bytecode, a total of six FUs have been developed for the Java processor, namely a frame stack, a heap manager, a thread scheduler, a debugger, an integer ALU and a floating-point unit. Using these FUs, the processor can already execute the SPEC JVM98 benchmark suite properly. This indicates that it can be employed to run a broad variety of applications rather than embedded software only. Besides bytecode execution, several enhanced features have also been implemented in the processor to improve its performance and usability. First, the processor includes an object cache using a novel cache index generation scheme that provides a better average hit rate than the classical XOR-based scheme. Second, a hardware garbage collector has been integrated into the heap manager, which greatly reduces the overhead caused by the garbage collection process. Third, thread scheduling has been realized in hardware as well, which allows it to be performed concurrently with the running application. Furthermore, a complete debugging framework has been developed for the processor, which provides powerful debugging functionalities at both software and hardware levels.
Item Type: | Ph.D. Thesis | ||||
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Erschienen: | 2019 | ||||
Creators: | Li, Changgong | ||||
Type of entry: | Primary publication | ||||
Title: | Implementation of an AMIDAR-based Java Processor | ||||
Language: | English | ||||
Referees: | Hochberger, Prof. Dr. Christian ; Karl, Prof. Dr. Wolfgang | ||||
Date: | 2019 | ||||
Place of Publication: | Darmstadt | ||||
Refereed: | 8 April 2019 | ||||
URL / URN: | https://tuprints.ulb.tu-darmstadt.de/8627 | ||||
Abstract: | This thesis presents a Java processor based on the Adaptive Microinstruction Driven Architecture (AMIDAR). This processor is intended as a research platform for investigating adaptive processor architectures. Combined with a configurable accelerator, it is able to detect and speed up hot spots of arbitrary applications dynamically. In contrast to classical RISC processors, an AMIDAR-based processor consists of four main types of components: a token machine, functional units (FUs), a token distribution network and an FU interconnect structure. The token machine is a specialized functional unit and controls the other FUs by means of tokens. These tokens are delivered to the FUs over the token distribution network. The tokens inform the FUs about what to do with input data and where to send the results. Data is exchanged among the FUs over the FU interconnect structure. Based on the virtual machine architecture defined by the Java bytecode, a total of six FUs have been developed for the Java processor, namely a frame stack, a heap manager, a thread scheduler, a debugger, an integer ALU and a floating-point unit. Using these FUs, the processor can already execute the SPEC JVM98 benchmark suite properly. This indicates that it can be employed to run a broad variety of applications rather than embedded software only. Besides bytecode execution, several enhanced features have also been implemented in the processor to improve its performance and usability. First, the processor includes an object cache using a novel cache index generation scheme that provides a better average hit rate than the classical XOR-based scheme. Second, a hardware garbage collector has been integrated into the heap manager, which greatly reduces the overhead caused by the garbage collection process. Third, thread scheduling has been realized in hardware as well, which allows it to be performed concurrently with the running application. Furthermore, a complete debugging framework has been developed for the processor, which provides powerful debugging functionalities at both software and hardware levels. |
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URN: | urn:nbn:de:tuda-tuprints-86275 | ||||
Classification DDC: | 000 Generalities, computers, information > 000 Generalities 000 Generalities, computers, information > 004 Computer science |
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Divisions: | 18 Department of Electrical Engineering and Information Technology 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering > Computer Systems Group |
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Date Deposited: | 21 Apr 2019 19:55 | ||||
Last Modified: | 21 Apr 2019 19:55 | ||||
PPN: | |||||
Referees: | Hochberger, Prof. Dr. Christian ; Karl, Prof. Dr. Wolfgang | ||||
Refereed / Verteidigung / mdl. Prüfung: | 8 April 2019 | ||||
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