Ernst, Markus ; Klupsch, Steffen ; Hauck, Oliver ; Huss, Sorin (2001)
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems.
Conference or Workshop Item, Bibliographie
Abstract
A generator-based design and validation methodology for rapid prototyping of elliptic curve public-key cryptosystem hardware is described. By their very nature, crypto systems challenge both design and validation. Pure RTL-based synthesis is as unsuitable as is high-level synthesis. Instead, a generator program accepts the two main parameters, key size and multiplier radix, and creates a highly efficient custom RTL description which is synthesized into a FPGA. This approach benefits the design in that it allows to effortlessly exploit the available resources on the FPGA for variable requirements of security and performance. It is also advantageous for validation of the correctness of the design as for small parameter values the design can be tested exhaustively. Thus, the correctness for large key sizes depends only on the correctness of the generator. Furthermore, deploying FPGAs supports integration of an ASIC realisation of the same algorithm which boosts performance...
| Item Type: | Conference or Workshop Item |
|---|---|
| Erschienen: | 2001 |
| Creators: | Ernst, Markus ; Klupsch, Steffen ; Hauck, Oliver ; Huss, Sorin |
| Type of entry: | Bibliographie |
| Title: | Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems |
| Language: | English |
| Date: | June 2001 |
| Book Title: | Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping |
| Abstract: | A generator-based design and validation methodology for rapid prototyping of elliptic curve public-key cryptosystem hardware is described. By their very nature, crypto systems challenge both design and validation. Pure RTL-based synthesis is as unsuitable as is high-level synthesis. Instead, a generator program accepts the two main parameters, key size and multiplier radix, and creates a highly efficient custom RTL description which is synthesized into a FPGA. This approach benefits the design in that it allows to effortlessly exploit the available resources on the FPGA for variable requirements of security and performance. It is also advantageous for validation of the correctness of the design as for small parameter values the design can be tested exhaustively. Thus, the correctness for large key sizes depends only on the correctness of the generator. Furthermore, deploying FPGAs supports integration of an ASIC realisation of the same algorithm which boosts performance... |
| Divisions: | 20 Department of Computer Science 20 Department of Computer Science > Integrated Circuits and Systems |
| Date Deposited: | 31 Dec 2016 00:15 |
| Last Modified: | 03 Jun 2018 21:31 |
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