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Field Effect Transistor Arrangement

Krauss, Tillmann ; Wessely, Frank ; Schwalke, Udo :
Technische Universität Darmstadt
Field Effect Transistor Arrangement.
[Online-Edition: https://patentscope.wipo.int/search/en/detail.jsf?docId=WO20...]
PCT/EP/2014/063459.
[Patent], (2014)

Offizielle URL: https://patentscope.wipo.int/search/en/detail.jsf?docId=WO20...

Kurzbeschreibung (Abstract)

The invention relates to a field effect transistor arrangement having a planar channel layer (1) consisting of semiconductor material, the whole surface of the underside of said layer being applied to an upper side of an electrically insulating substrate layer (2) and the upper side of said planar channel layer being covered by an insulation layer (3). The arrangement has a source electrode (6) on a first side edge of the channel layer (1) and a drain electrode (7) on a second side edge of the channel layer (1) and a control electrode (9) arranged above the channel layer (1). An adjusting electrode (5) is arranged on an underside of the substrate layer (2). A contact region (8) between the source and drain electrodes (6) and the planar channel layer (1) is in each case configured as a midgap Schottky barrier. A respective barrier control electrode (10) is arranged in the vicinity of the contact region (8) of the source electrode (6) and of the drain electrode (6). Each barrier control electrode (10) can have a section (11) that projects outwards in the direction of the planar channel layer (1).

Typ des Eintrags: Patent
Erschienen: 2014
Autor(en): Krauss, Tillmann ; Wessely, Frank ; Schwalke, Udo
Titel: Field Effect Transistor Arrangement
Sprache: Englisch
Kurzbeschreibung (Abstract):

The invention relates to a field effect transistor arrangement having a planar channel layer (1) consisting of semiconductor material, the whole surface of the underside of said layer being applied to an upper side of an electrically insulating substrate layer (2) and the upper side of said planar channel layer being covered by an insulation layer (3). The arrangement has a source electrode (6) on a first side edge of the channel layer (1) and a drain electrode (7) on a second side edge of the channel layer (1) and a control electrode (9) arranged above the channel layer (1). An adjusting electrode (5) is arranged on an underside of the substrate layer (2). A contact region (8) between the source and drain electrodes (6) and the planar channel layer (1) is in each case configured as a midgap Schottky barrier. A respective barrier control electrode (10) is arranged in the vicinity of the contact region (8) of the source electrode (6) and of the drain electrode (6). Each barrier control electrode (10) can have a section (11) that projects outwards in the direction of the planar channel layer (1).

Fachbereich(e)/-gebiet(e): Fachbereich Elektrotechnik und Informationstechnik
Fachbereich Elektrotechnik und Informationstechnik > Institut für Halbleitertechnik und Nanoelektronik
Hinterlegungsdatum: 19 Apr 2016 12:50
Offizielle URL: https://patentscope.wipo.int/search/en/detail.jsf?docId=WO20...
ID-Nummer: PCT/EP/2014/063459
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