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Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

Hempel, Gerald and Hoyer, Jan and Pionteck, Thilo and Hochberger, Christian (2013):
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs.
In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1-6, [Online-Edition: http://dx.doi.org/10.1109/ReCoSoC.2013.6581522],
[Conference or Workshop Item]

Item Type: Conference or Workshop Item
Erschienen: 2013
Creators: Hempel, Gerald and Hoyer, Jan and Pionteck, Thilo and Hochberger, Christian
Title: Register allocation for high-level synthesis of hardware accelerators targeting FPGAs
Language: English
Title of Book: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
Divisions: 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering > Computer Systems Group
18 Department of Electrical Engineering and Information Technology
18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering
Date Deposited: 19 Apr 2016 07:25
Official URL: http://dx.doi.org/10.1109/ReCoSoC.2013.6581522
Identification Number: doi:10.1109/ReCoSoC.2013.6581522
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