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GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs

Vogt, Markus and Hempel, Gerald and Castrillon, Jeronimo and Hochberger, Christian (2015):
GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs.
In: Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP), In: FSP 2015, [Conference or Workshop Item]

Abstract

In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular. Such hybrid architectures allow extending embedded software with application specific hardware accelerators to improve performance and/or energy efficiency. Aiding system designers and programmers at handling the complexity of the required process of hardware/software (HW/SW) partitioning is an important issue. Current methods are often restricted, either to bare-metal systems, to subsets of mainstream programming languages, or require special coding guidelines, e.g., via annotations. These restrictions still represent a high entry barrier for the wider community of programmers that new hybrid architectures are intended for. In this paper we revisit HW/SW partitioning and present a seamless programming flow for unrestricted, legacy C code. It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly. The proposed workflow was evaluated on the Xilinx Zynq platform using unmodified code from an embedded benchmark suite.

Item Type: Conference or Workshop Item
Erschienen: 2015
Creators: Vogt, Markus and Hempel, Gerald and Castrillon, Jeronimo and Hochberger, Christian
Title: GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs
Language: English
Abstract:

In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular. Such hybrid architectures allow extending embedded software with application specific hardware accelerators to improve performance and/or energy efficiency. Aiding system designers and programmers at handling the complexity of the required process of hardware/software (HW/SW) partitioning is an important issue. Current methods are often restricted, either to bare-metal systems, to subsets of mainstream programming languages, or require special coding guidelines, e.g., via annotations. These restrictions still represent a high entry barrier for the wider community of programmers that new hybrid architectures are intended for. In this paper we revisit HW/SW partitioning and present a seamless programming flow for unrestricted, legacy C code. It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly. The proposed workflow was evaluated on the Xilinx Zynq platform using unmodified code from an embedded benchmark suite.

Series Name: FSP 2015
Divisions: 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering > Computer Systems Group
18 Department of Electrical Engineering and Information Technology
18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering
Event Title: Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP)
Date Deposited: 19 Apr 2016 07:25
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