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Optimizing the Memory Access Performance of FASTEST's Sispol Routine

Burger, Michael ; Bischof, Christian (2014)
Optimizing the Memory Access Performance of FASTEST's Sispol Routine.
World Congress on Computational Mechanics. Barcelona, Spain
Konferenzveröffentlichung, Bibliographie

Kurzbeschreibung (Abstract)

In this article the runtime behavior of the simulation software Fastest is investigated and its performance is optimized. The main performance bottleneck of Fastest is the sipsol subroutine. An analysis shows that the memory accessing behavior is the main reason for the high runtime. As a consequence, a new data structure is developed which on the one hand increases the speed but on the other hand preserves the ability to parallelize the calculations on the data grid executed within the sipsol subroutine. The ratio between calculation and memory reads/writes is improved significantly, and the performance in certain cases doubled. Finally, approaches to efficiently implement a parallelization within the new structure are proposed.

Typ des Eintrags: Konferenzveröffentlichung
Erschienen: 2014
Autor(en): Burger, Michael ; Bischof, Christian
Art des Eintrags: Bibliographie
Titel: Optimizing the Memory Access Performance of FASTEST's Sispol Routine
Sprache: Englisch
Publikationsjahr: Juli 2014
Band einer Reihe: 11
Veranstaltungstitel: World Congress on Computational Mechanics
Veranstaltungsort: Barcelona, Spain
URL / URN: http://www.wccm-eccm-ecfd2014.org/admin/files/filePaper/p153...
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Kurzbeschreibung (Abstract):

In this article the runtime behavior of the simulation software Fastest is investigated and its performance is optimized. The main performance bottleneck of Fastest is the sipsol subroutine. An analysis shows that the memory accessing behavior is the main reason for the high runtime. As a consequence, a new data structure is developed which on the one hand increases the speed but on the other hand preserves the ability to parallelize the calculations on the data grid executed within the sipsol subroutine. The ratio between calculation and memory reads/writes is improved significantly, and the performance in certain cases doubled. Finally, approaches to efficiently implement a parallelization within the new structure are proposed.

Schlagworte:
Einzelne SchlagworteSprache
Data Structures, Performance Optimization, Parallelization, Cache OptimizationEnglisch
Fachbereich(e)/-gebiet(e): 20 Fachbereich Informatik
20 Fachbereich Informatik > Scientific Computing
Exzellenzinitiative
Exzellenzinitiative > Graduiertenschulen
Exzellenzinitiative > Graduiertenschulen > Graduate School of Computational Engineering (CE)
Zentrale Einrichtungen
Zentrale Einrichtungen > Hochschulrechenzentrum (HRZ)
Zentrale Einrichtungen > Hochschulrechenzentrum (HRZ) > Hochleistungsrechner
Hinterlegungsdatum: 26 Mär 2015 12:32
Letzte Änderung: 07 Jan 2021 10:00
PPN:
Schlagworte:
Einzelne SchlagworteSprache
Data Structures, Performance Optimization, Parallelization, Cache OptimizationEnglisch
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